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AR# 64615

MIG - UltraScale - AXI Interface efficiency improvements for 2015.2

Description

Version Found: v7.1

Version Resolved: See (Xilinx Answer 58435)

The product guide recommends ROW_COLUMN_BANK for the ordering of the memory controller.

Due to changes in the MIG controller for UltraScale, this will cause low performance for AXI interfaces.

Solution

To improve the efficiency of the AXI interface, the parameter AUTO_AP_COL_A3 should be set to "ON" in the RTL located in the files below.

You will need to update the file which matches the memory type you have selected:

  • DDR3- mig_v7_1_ddr3_mem_intfc.sv
  • DDR4 - mig_v7_1_ddr4_mem_intfc.sv

Revision History:

06/25/2015 - Initial Release

AR# 64615
Date Created 05/19/2015
Last Updated 10/01/2015
Status Active
Type Known Issues
IP
  • MIG UltraScale