UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 64615

UltraScale DDR4/DDR3 - AXI Interface efficiency improvements for 2015.2

Description

Version Found: DDR4 v7.1, DDR3 v7.1

Version Resolved: See (Xilinx Answer 69035) for DDR4, See (Xilinx Answer 69036) for DDR3

The product guide recommends ROW_COLUMN_BANK for the ordering of the memory controller.

Due to changes in the MIG controller for UltraScale, this will cause low performance for AXI interfaces.

Solution

To improve the efficiency of the AXI interface, the parameter AUTO_AP_COL_A3 should be set to "ON" in the RTL located in the files below.

You will need to update the file which matches the memory type you have selected:

  • DDR3- mig_v7_1_ddr3_mem_intfc.sv
  • DDR4 - mig_v7_1_ddr4_mem_intfc.sv

Revision History:

06/25/2015 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
69036 UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues N/A N/A
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
AR# 64615
Date 01/02/2018
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Virtex UltraScale
Tools
  • Vivado Design Suite - 2015.1
IP
  • MIG UltraScale
Page Bookmarked