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AR# 64632

Virtex-7 FPGA GEN3 Integrated Block for PCI Express - How to enable 64 bit Prefetchable Memory Base/Limit Registers in TYPE1 Config Space?

Description

When the Virtex-7 FPGA GEN3 Integrated Block for PCI Express core is configured as Root Port, the Prefetchable Memory Base/Limit Registers in TYPE1 Config Space are enabled with only 32 bits by default.

How do I enable the 64-bit option?

Solution

To enable 64 bit Prefetchable Memory Base/Limit Registers in TYPE1 Config Space, write 32h60000 to the register at address 400C0 through the configuration management interface. 

Make sure that cfg_mgmt._addr [18] is set to 1.

cfg_mgmt_addr <= #TCQ 32'h400C0;

cfg_mgmt_write_data <= #TCQ 32'h60000;

You can verify the result by reading the Prefetchable Memory Base/Limit Registers at address 9 (byte address 32h'24). 

If the last 4 bits are 4h0, then it only supports 32-bit.

If it is 4h1, this indicates that 64-bit is successfully enabled.

Revision History:
06/10/2015 - Initial Release
AR# 64632
Date Created 05/20/2015
Last Updated 06/30/2015
Status Active
Type General Article
IP
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)