When the Virtex-7 FPGA GEN3 Integrated Block for PCI Express core is configured as Root Port, the Prefetchable Memory Base/Limit Registers in TYPE1 Config Space are enabled with only 32 bits by default.
How do I enable the 64-bit option?
To enable 64 bit Prefetchable Memory Base/Limit Registers in TYPE1 Config Space, write 32h60000 to the register at address 400C0 through the configuration management interface.
Make sure that cfg_mgmt._addr  is set to 1.
You can verify the result by reading the Prefetchable Memory Base/Limit Registers at address 9 (byte address 32h'24).
If the last 4 bits are 4h0, then it only supports 32-bit.
If it is 4h1, this indicates that 64-bit is successfully enabled.