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AR# 64698

2015.2 Vivado - VHDL Configuration architecture does not show up correctly in the Vivado hierarchy window

Description

The Vivado Hierarchy Source View (HSV) does not properly display configuration architectures.

For example, I have the following configuration:

mux_arch.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

architecture ARCH_COMBINATIONAL1 of mux_ent is
begin
  with(Sel(1 downto 0)) select
    MUX_OUT <= Data(0) when "00",
          Data(1) when "01",
          Data(2) when "10",
          Data(3) when "11",
          'X'      when others;
end architecture ARCH_COMBINATIONAL1;

architecture ARCH_COMBINATIONAL2 of mux_ent is
begin
  COMB_PROCESS : process(Sel(1 downto 0),Data(3 downto 0) )
  begin
    case (Sel(1 downto 0)) is
      when "00" =>
        MUX_OUT <= Data(0);
      when "01" =>
       MUX_OUT <= Data(1);
      when "10" =>
        MUX_OUT <= Data(2);
      when "11" =>
        MUX_OUT <= Data(3);
      when others =>
        MUX_OUT <= 'X';
    end case;
  end process COMB_PROCESS;
end architecture ARCH_COMBINATIONAL2;

architecture ARCH_COMBINATIONAL3 of mux_ent is
begin
  MUX_OUT <= Data(to_integer(unsigned(Sel)));
end architecture ARCH_COMBINATIONAL3;

architecture ARCH_SEQUENTIAL1 of mux_ent is
  signal Y : std_logic := '0';
begin

  SEQ_PROCESS : process(CLK)
  begin
    if(rising_edge(CLK)) then     
      if(RST = '1') then
        Y <= '0';
      else
        Y <= Data(to_integer(unsigned(Sel)));
      end if;
    end if;     
  end process SEQ_PROCESS;
  MUX_OUT <= Y;
end architecture ARCH_SEQUENTIAL1;

architecture ARCH_SEQUENTIAL2 of mux_ent is
  signal Y : std_logic := '0';
begin
  SEQ_PROCESS : process(CLK)
  begin
    if(rising_edge(CLK)) then     
      if(iRST = '1') then
        Y <= '0';
      else
        case (Sel(1 downto 0)) is
          when "00" =>
            Y <= Data(0);
          when "01" =>
            Y <= Data(1);
          when "10" =>
            Y <= Data(2);
          when "11" =>
            Y <= Data(3);
          when others =>
            Y <= 'X';
        end case;
      end if;
    end if;     
  end process SEQ_PROCESS;
  MUX_OUT <= Y;
end architecture ARCH_SEQUENTIAL2;

mux_config.vhd
configuration config_mux of mux_top is
  for struct_top -- architecture of mux_top_ent
    for mux_ent_U1 : mux_ent
      use entity work.mux_ent(ARCH_SEQUENTIAL1);
    end for;
  end for;
end configuration config_mux;


  • mux_ent.vhd only shows up in compile order but not in the Sources -> Hierarchy window.
  • No matter which architecture is selected in mux_config.vhd, the Sources -> Hierarchy window always shows that ARCH_SEQUENTIAL2 is selected.  (Note however that the tools seem to use the correct architecture specified during synthesis).
  •      For example,  In mux_config.vhd, I change the architecture name to ARCH_COMBINATIONAL1, ARCH_COMBINATIONAL2, ARCH_COMBINATIONAL3 but hierarchy is always shown for ARCH_SEQUENTIAL2

Solution

The Vivado HSV supports configuration specifications, but not configuration declarations.

With a specification you could write a VHDL testbench that uses the desired architecture for the entity to be instantiated, but this is not as flexible as using a configuration declaration.

To work around this limitation in Vivado 2015.2 or earlier, you can put the Hierarchy Source View (HSV) in manual compile order and order the files as you wish.

In Vivado 2015.3 Vivado HSV has been enhanced to properly parse and display configuration declarations.

HSV will no longer move configuration files into the unreferenced folder. However, you should make sure to select the configuration as "top".

AR# 64698
Date Created 05/28/2015
Last Updated 10/06/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2015.2
  • Vivado Design Suite - 2015.1
  • Vivado Design Suite - 2014.1
  • Vivado Design Suite - 2013.1