I have set an HDL module as "Out of Context (OOC) for synthesis.
However, it is now also treated as a black box for simulation.
The elaboration for simulation indicates that the module is treated as a black box and the simulation shows the outputs of the module as undefined (x).
Running behavioral simulation from Flow Navigator shows the outputs of my_mod as X.
the Simulation compile order is not returning the OOC file from the fileset:
The get_files -compile_order code should work for stitching together files across OOC blocks and other HDL.
Until this is fixed, two ways to work around the issue are:
set_param project.addBlockFilesetFilesForUnifiedSim 1