Version Found: v4.0 (Vivado 2015.1)
Version Resolved and other Known Issues: See (Xilinx Answer 57945)
When generating UltraScale FPGA Gen3 Integrated Block for PCI Express core for the following devices, the generated XDC file consists of incorrect refclk_buf locations.
This is a known issue to be fixed in the next release of the core.
Please correct the constraints as follows:
Note: The "Version Found" column lists the version the problem was first discovered.The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions.