There is only one Reconfigurable Partition (RP) in my Partial Reconfiguration design.
I am using the same netlist file for 2 Reconfigurable Modules (RM1 and RM2) of the RP.
The first RM implementation completes without error.
I carve RM1 and import the netlist of RM2.
Phase 2 Global Placement
ERROR: [Place 30-504] Global clock placer failed to legalize CLOCKREGION_X0Y7 for clock loads of type DSP48E1. This region contains 120 available DSP48E1 sites,
however there are 526 such loads in the region and clock legalizer could not move enough loads out of the region to legalize it.
The following clock nets have loads of type DSP48E1 in this region:
Clock net: ext_clk.pipe_clock_i/CLK_USERCLK2
Number of DSP48E1 loads: 120
After setting the skipUtilizationCheck parameter and rerunning placement, I see a new place error.
ERROR: [Place 30-818] Some BRAM area constraints are over utilized.
148 or more BRAMs failed to place.
Some BRAM sites are excluded by the following pblocks. Check whether sufficient sites exist for BRAM instances not included in the exclude pblocks.
Exclude pblock 'pblock_reconfig_module': with ranges:
The unplaced BRAMs
are constrained as below: (listing maximum of 20 BRAMs per constraint)
Number of BRAMs required by this constraint: 508
Number of BRAMs available in this constraintregion: 275
The original available BRAM in 'pblock_reconfig_module is 1880, much more than 275.