Implementation Fails due to this missing CLK.
This is a known issue in Vivado 2015.1, as it blocks debugging of signals inside ChipScope cores.
To work around this issue, do one of the following:
1. After the Set Up Debug step is completed and when the Critical Warning is seen, manually add the clock using the following Tcl command:
connect_debug_port u_ila_0/clk [get_nets [list c0_rld3_ui_clk ]]
2. Alternatively, use this set_param before the Setup Debug step:
This issue is fixed in Vivado 2015.2.