AR# 64764: Vivado Logic Analyzer - Warning: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3
Vivado Logic Analyzer - Warning: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3
When programming the device in Hardware Manager for a design with ILA, I receive the following warnings:
WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4.
WARNING: [Labtools 27-1974] Mismatch between the design programmed into the device <device_name> and the probes file <file_name.ltx>.
How can I resolve this issue?
The clock net connected to dbg_hub is automatically selected by the tool based on the debug core configuration and connections.
However, you can change this clock net by modifying the "connect_debug_port" command in XDC.
The following are possible causes and solutions:
1. The clock that is connected to dbg_hub is a non-free-running clock.
To check which clock net is connected to the dbg_hub, follow these steps in the Vivado GUI: Open the Synthesized design or Implemented design -> Right click the dbg_hub core in the netlist hierarchy and select "Schematic" -> Double click the "clk" pin
If this clock is a non-free-running clock, change it to a free running one by modifying this command in XDC: