Version Found: MIG UltraScale v7.0
Version Resolved: See (Xilinx Answer 58435)
MIG UltraScale DDR4 and DDR3 IP designs have an "Enable Chip Select Pin" option in the customization GUI which enables or disables generation and use of the Chip Select Pin.
If this option is disabled and the MIG IP is generated, when the IP is customized again the GUI incorrectly shows that Chip Select is Enabled.
This is only an issue with the MIG customization GUI as the MIG IP generates correctly and has Chip Select Disabled.
However, if Chip Select needs to be enabled again, you must first uncheck (disable) the Chip Select Pin option and then enable it again.
Revision History:
06/30/2015 - Initial Release
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 58435 | DDR4, DDR3, QDRIV, QDRII+, RLDRAM3, LPDDR3 UltraScale and UltraScale+ - IP Release Notes and Known Issues | N/A | N/A |
| AR# 64773 | |
|---|---|
| Date | 06/30/2015 |
| Status | Active |
| Type | Known Issues |
| Devices |
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| IP |
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