Version Found: DDR3 v7.1
Version Resolved: See (Xilinx Answer 69036)
The following tZQinit violations might be seen during DDR3 simulations when using the Micron memory model:
These violations are the result of an issue with the Micron memory model and not the MIG IP.
These violations can be safely ignored because the violations will not occur during hardware.
Please contact Micron for a solution with their memory model.
06/30/2015 - Initial Release