AR# 64775

UltraScale DDR3 - tZQinit violations seen during DDR3 simulations


Version Found: DDR3 v7.1

Version Resolved: See (Xilinx Answer 69036)

The following tZQinit violations might be seen during DDR3 simulations when using the Micron memory model:

# sim_tb_top.mem_model_x8.memRank[0].memModel[1].u_ddr3_x8.chk_err: at time 5544836.0 ps ERROR: tZQinit violation during Activate

# sim_tb_top.mem_model_x8.memRank[0].memModel[0].u_ddr3_x8.main: at time 5533970.0 ps ERROR: TZQinit violation during ODT transition


These violations are the result of an issue with the Micron memory model and not the MIG IP.

These violations can be safely ignored because the violations will not occur during hardware.

Please contact Micron for a solution with their memory model.

Revision History:

06/30/2015 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
69036 UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues N/A N/A
AR# 64775
Date 01/02/2018
Status Active
Type Known Issues