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AR# 64777

Vivado Synthesis - SystemVerilog case inside range expression support

Description

When synthesizing my design, I find the following error when using a SystemVerilog case inside statement:

Error:[Synth 8-26] range choice in case statement not implemented

Error:[Synth 8-285] failed synthesizing module 'test'

The code is below:

always @ (posedge clk)   
    case (sel) inside
        [1:0]: reg_out <= data_a;
        [3:2]: reg_out <= data_b;
       endcase

Solution

Support for a SystemVerilog case inside a range expression [#:#] will be added in a future release.

Currently a supported version of this code would be as follows:

always @ (posedge clk)   
    case (sel) inside
        0,1: reg_out <= data_a;
        2,3: reg_out <= data_b;
       endcase

AR# 64777
Date 04/19/2017
Status Active
Type Known Issues
Tools
  • Vivado Design Suite
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