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AR# 64787

7 Series FPGAs Transceiver Wizard v3.5 Rev1 - Release Notes and Known Issues

Description

This answer record contains the Release Notes and Known Issues for the 7 series FPGAs Transceiver Wizard v3.5 Rev1 released with the Vivado 2015.2 design tool.

Solution


Issue 1: 7 Series GTX wizard "generate output products" error message for a specific configuration.

Description: When trying to generate a GTX core at 0.5 Gbps line rate with the 7 series GTX wizard, the following error occurs.

This happens only for the external/internal data width combination of 64/32 or 80/40:

ERROR: [#UNDEF] Caught exception Could not find any valid vcoRates for 7.8125
CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2014.4/data/ip/xilinx/gtwizard_v3_4/ttcl/instantiation_template.ttcl':
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
ERROR: [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'gtwizard_8'. Failed to generate 'Verilog Instantiation Template' outputs:
ERROR: [IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'gtwizard_8'. Failed to generate 'Verilog Instantiation Template' outputs

To be fixed version: 2015.3


Issue 2: The GT wizard resets the frame generator at the completion of RXRESETDONE instead of waiting for the rx_startup state machine to complete.

Description: The GT wizard resets the frame generator at the completion of RXRESETDONE instead of waiting for the rx_startup state machine to complete.

In a design that uses buffer bypass, it should wait for the buffer alignment to complete before performing the system reset.

Workaround: Bring the phasealignment_done signal from the <component_name>_init.v/vhd file to the top level and change the following line:

assign gt0_rx_system_reset_c = !gt0_rxresetdone_r3;

to:

assign gt0_rx_system_reset_c = !gt0_rxphasealignmentdone_r3;

To be fixed version: 2015.3


Issue 3: PCS_RSVD_ATTR[8] is set incorrectly for GTH wizard if OOB is selected.

Description: PCS_RSVD_ATTR[8] should be set to 1'b1 if 'Use RX OOB Signal Detection' is checked in the GUI for GTH designs.

Workaround: Change the attribute value to: PCS_RSVD_ATTR (48'h000000000100)

To be fixed version: 2015.3


Issue 4: GTZ wizard example design fails in hardware when using raw encoding.

Description: GTZ wizard example design is unable to maintain DC balance when using RAW encoding and hence designs are failing in board.

Workaround: Use the PRBS_ANY PRBS generator from XAPP884. 

Connect gen to the transceiver TXDATA and RXDATA to a checker.

To Be fixed version: 2015.3

Revision History:

06/12/2015 - Initial Release

AR# 64787
Date Created 06/12/2015
Last Updated 10/01/2015
Status Active
Type Release Notes
Tools
  • Vivado Design Suite - 2015.2
IP
  • 7 Series FPGAs Transceivers Wizard