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AR# 64856

Design Advisory for UltraScale DDR4/DDR3 - PCB pull-down required on the DDR3 RESET# pin and on the DDR4 RESET_N pin to maintain logic low during memory initialization


This Design Advisory covers the UltraScale DDR4/DDR3 IP. 

Currently, the board guidelines documented in (PG150) UltraScale Architecture FPGAs Memory Solutions and (UG583) UltraScale Architecture PCB Design do not include a recommendation on the DDR3 RESET# or DDR4 RESET_N pins. 

This Design Advisory is being released to alert users to the required pull-down on RESET# and/or RESET_N.


The RESET# and RESET_N signals should not be terminated.

The DDR3 and DDR4 JEDEC standards require RESET# and RESET_N to be pulled low during memory initialization. 

The recommendation for this pull down is a 4.7 kohm resistor connected to GND.

During initialization, if termination occurs instead of the required pull-down on RESET# or RESET_N, it can cause the SDRAM to initialize to an unexpected state.

In the case of DDR4, the SDRAM has come up in a test mode which causes calibration to act similarly on one power cycle and then fail differently after a power cycle.

This pull-down information will be added to both (PG150) and (UG583) in the next revision of these documents.

Revision History:
07/06/15 - Initial Release

Linked Answer Records

Master Answer Records

AR# 64856
Date 07/03/2015
Status Active
Type Design Advisory
  • Kintex UltraScale
  • Virtex UltraScale
  • MIG UltraScale