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AR# 64866

v2015.1 - Migrating XAPP1198 to v2015.1 causes Validation errors for FREQ_HZ


Migrating XAPP1198 to v2015.1 causes Validation errors for FREQ_HZ.

Error [BD 41-237] Bus Interface property FREQ_HZ does not match between <> and <>


The issue here is that the parameter CONFIG.FREQ_HZ is not set at the source of the AXI_aclk clock.

Because the PCIe core where AXI_aclk clock is originated is residing outside of the Block diagram (regular non-BD core), it does not set this property as its not needed unless it is a Block Diagram (BD) design.

The parameter in this case is set at the input port AXI_aclk in the BD design because that is the source from the BD design perspective.

To fix this issue, follow the steps below:

1) In the BD design, remove the current AXI_aclk port (just delete the port but keep the clock net)

2) Create a new port (right click on the empty space in the BD design and choose Create Port)

3) Give the Port name AXI_aclk, change the Type to Clock. 

Set the Frequency to 125 as this ext_ch_gt_drpclk is a 125MHz clock in your design (connected to CLKOUT3 of the MMCM with clock name userclk2)

4) Connect the new port to the existing clock net in the BD design.

5) Validate the BD.

AR# 64866
Date 07/15/2015
Status Active
Type General Article
  • Vivado Design Suite - 2015.1
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