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AR# 64873

Vivado Synthesis - Gated clock conversion is not supported if the gated clock is driving logics across a preserved hierarchy boundary


When the gated clock is driving logics across the hierarchy boundaries preserved by the "-flatten_hierarchy none" or keep_hierarchy/dont_touch attributes, the gated clock conversion is not successful.

How can I resolve the gated clock conversion in this case?


Gated clock conversion across solid hierarchy boundaries is not supported.

The following are some example use cases:

  1. -flatten_hierarchy is set to none and the gated clock is driving logics within another hierarchy.
  2. The gated clock is driving IPs generated from IP Catalog.
    Because the dont_touch attribute is applied to the IP boundaries during Synthesis, the IP top hierarchies are preserved.
  3. The gated clock is driving logics within another hierarchy which is preserved by a keep_hierarchy or dont_touch attribute.

You can use the following work-arounds in these cases:

  1. Manually do gated clock conversion in the RTL code.
  2. Avoid doing gated clock conversion for those clocks if the clock frequency is not too high to meet timing requirements.
    Add a create_generated_clock constraint for the gated clock in XDC.
AR# 64873
Date 07/06/2015
Status Active
Type General Article
  • Vivado Design Suite
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