I have a simple project that passes synthesis.
However, if I make an address change in the Block Design and re-run synthesis, this fails with an error similar to the following:
How can I resolve this?
In Vivado 2015.2, if there is a change in the BD, the tools will automatically regenerate the IP during synthesis. However, in some cases, this is not happening.
To work around this issue, you can do the following:
In Vivado 2015.3, a check was added in the code to see if the block fileset run already exists but is STALE or NOT complete. If so, the run is reset.
These runs will then get pulled through as part of running the top level synthesis run.
In earlier versions, these block runs were marked as DONE but
STALE. By design, the pull through code does not automatically rerun
anything that is DONE and STALE.