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AR# 64874

2015.2 Vivado IP Flows - Synthesis fail after making changes within the Block Design (BD)


I have a simple project that passes synthesis. 

However, if I make an address change in the Block Design and re-run synthesis, this fails with an error similar to the following:

[Synth 8-549] port width mismatch for port 's_axi_awaddr': port width = 13, actual width = 14 ["<PATH>/project_1/project_1.srcs/sources_1/bd/base_zynq_design/hdl/base_zynq_design.vhd":2140]
[Synth 8-285] failed synthesizing module 'base_zynq_design' ["<PATH>/project_1/project_1.srcs/sources_1/bd/base_zynq_design/hdl/base_zynq_design.vhd":1810]
[Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

How can I resolve this?


In Vivado 2015.2, if there is a change in the BD, the tools will automatically regenerate the IP during synthesis. However, in some cases, this is not happening.

To work around this issue, you can do the following:

  • A. Save the Block design Prior to running Synthesis
  • B. Run Reset output products before running Synthesis

In Vivado 2015.3, a check was added in the code to see if the block fileset run already exists but is STALE or NOT complete.  If so, the run is reset.  

These runs will then get pulled through as part of running the top level synthesis run.

In earlier versions, these block runs were marked as DONE but STALE. By design, the pull through code does not automatically rerun anything that is DONE and STALE.

AR# 64874
Date 05/03/2016
Status Archive
Type General Article
  • Vivado Design Suite - 2015.1
  • Vivado Design Suite - 2015.2
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