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AR# 64892

2014.3: Using generated block design Tcl gives validation error


I have generated a block design Tcl for my Zynq design.

I am trying to use the block design TCL to create the block design in another project, however, the I am receiving the following error:


ERROR: [IP_Flow 19-3478] Validation failed for parameter CLKPARAM (PCW_UART_PERIPHERAL_DIVISOR0)' with value '1' for BD Cell '/processing_system7_0'. Error: 1000.000 MHz Frequency is out of range for the parameter: PCW_UART_PERIPHERAL_FREQMHZ. Valid input frequency range is [10.000 : 100.000] MHz

What is the cause of this error?




This is a known issue in 2014.3 which is fixed in later versions.

When the block design Tcl is generated, UART divisor configuration is not included.


To work around this issue, add the "CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10}" manually to the processing_system7_0 set_property list in the block design Tcl which is generated.


AR# 64892
Date 07/16/2015
Status Archive
Type Known Issues
  • Zynq-7000
  • Vivado Design Suite - 2014.3
  • Processing System 7
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