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AR# 64923

MIG UltraScale - Hardware Manager Xicom error messages occuring after programming device

Description

Version Found: MIG UltraScale v7.0

Version Resolved: See (Xilinx Answer 58435)

After programming the device, the following error message can occur in the 2015.1 version of Hardware Manager:

ERROR: [Xicom 50-38] xicom: ERROR: [Xicom 50-24] File /opt/Xilinx/Vivado/2015.1/data/xicom/mig_calibration_ddr3_0.csv does not exist.

 

 

ERROR: [Xicom 50-38] xicom: Data structures not initialized for CseXsdb slave Device:0, user chain number/bus:1, slave in

 

 

The following warning message might occur in the 2015.2 version of Hardware Manager or later:

WARNING: [Xicom 50-46] One or more detected MIG version registers have empty values: MIG properties will not be built.
Parameter Map Version: 1, Error Map Version: 0, Calibration Map Version: 0, Warning Map Version: 0
Invalid calibration version register value detected from MIG core: 000

 

These messages can occur when the required *.bmm and *.elf files built within the MIG IP are not properly associated during implementation.

If the *.elf and *.bmm files are not associated correctly, then the BRAM INIT values do not get stored correctly which will cause hardware failures.

Solution

Vivado 2015.1 and 2015.2

This issue can occur when using a MIG *.dcp instead of the *.xci as a result of the *.elf and *.bmm file association occurring incorrectly.

To resolve the issue, add the following commands to your scripts or project flow to properly associate the files to your design:

2015.1:

Elf Association

add_files /<location of *.elf file>/calibration_ddr.elf
set_property SCOPED_TO_REF <mig_inst_name> [get_files /<location of *.elf file>/calibration_ddr.elf]
set_property SCOPED_TO_CELLS inst/u_ddr_mc_cal/u_ddr_cal/mcs0/microblaze_I [get_files /<location of *.elf file>/calibration_ddr.elf]

 

BMM Association

add_files /<location of *.bmm file>/microblaze_mcs_ddr.bmm
set_property SCOPED_TO_REF <mig_inst_name> [get_files /<location of *.elf file>/microblaze_mcs_ddr.bmm]
set_property SCOPED_TO_CELLS inst/u_ddr_mc_cal/u_ddr_cal/mcs0 [get_files /<location of *.elf file>/microblaze_mcs_ddr.bmm]

 

2015.2:

ELF Association

add_files /<location of *.elf file>/calibration_ddr.elf
set_property SCOPED_TO_REF <mig_inst_name> [get_files *.elf]
set_property SCOPED_TO_CELLS {inst/u_ddr_cal_riu/mcs0/microblaze_I} [get_files /<location of *.elf file>/calibration_ddr.elf]

 

BMM Association

add_files /<location of *.elf file>/microblaze_mcs_ddr.bmm
set_property SCOPED_TO_REF <mig_inst_name> [get_files /<location of *.elf file>/microblaze_mcs_ddr.bmm]
set_property SCOPED_TO_CELLS {inst/u_ddr_cal_riu/mcs0/} [get_files /<location of *.elf file>/microblaze_mcs_ddr.bmm]

 

Vivado 2015.3 or Later:

This issue has additionally been seen in later versions of Vivado when .elf and .bmm files are not properly built into the design due to improper usage of the memory IP, the IP output files not being generated, an IP Integrator Block Diagram is being used with Memory IP, or when multiple Memory IP instances exist in the same design.

To verify if the memory IP .elf and .bmm files are associated properly, the Vivado log file should have an info message similar to the following.  

This message can also be seen when running refresh_design from the Tcl prompt:

INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: ../mig_0_example.srcs/sources_1/ip/mig_0/sw/calibration_0/Debug/calibration_ddr.elf

If this message is not present, the .elf and .bmm files were not associated properly and the following message will occur within Hardware Manager:

WARNING: [Xicom 50-46] One or more detected MIG version registers have empty values: MIG properties will not be built.
Parameter Map Version: 1, Error Map Version: 0, Calibration Map Version: 0, Warning Map Version: 0
Invalid calibration version register value detected from MIG core: 000

The .elf and .bmm files are located in the following directories of the generated Memory IP core:

  • core_name.srcs\sources_1\ip\ddr4_32_bit\sw\microblaze_mcs_ddr.bmm
  • core_name.srcs\sources_1\ip\ddr4_32_bit\sw\calibration_0\Debug\calibration_ddr.elf

The files can be added to the project and properly associated with Tcl commands similar to the following:

add_files /<location of *.elf file>/calibration_ddr.elf
add_files /<location of *.bmm file>/microblaze_mcs_ddr.bmm
set_property SCOPED_TO_REF core_name_ddr4_mem_intfc [get_files *.elf]
set_property SCOPED_TO_CELLS {u_ddr_cal_riu/mcs0/microblaze_I} [get_files *.elf]
set_property SCOPED_TO_REF core_name_ddr4_mem_intfc [get_files *.bmm]
set_property SCOPED_TO_CELLS {u_ddr_cal_riu/mcs0} [get_files *.bmm]

If using a Tcl script to build the design, ensure that both read_ip and generate_target commands are used for the Memory IP.

If using multiple Memory IP in the same design make sure to add each unique BMM and ELF file and then use absolute hierarchy paths in the SCOPED_TO_CELLS constraints instead of using the SCOPED_TO_REF constraint. 

If each Memory IP instance uses the same BMM and ELF files then make sure they are included as a list into a single SCOPED_TO_CELLS constraint.

For example:

add_files /<location of *.elf file>/calibration_ddr.elf
add_files /<location of *.bmm file>/microblaze_mcs_ddr.bmm
set_property SCOPED_TO_CELLS {<inst0>/u_ddr_cal_riu/mcs0/microblaze_I <inst1>/u_ddr_cal_riu/mcs0/microblaze_I <inst2>/u_ddr_cal_riu/mcs0/microblaze_I <inst3>/u_ddr_cal_riu/mcs0/microblaze_I} [get_files calibration_ddr.elf]
set_property SCOPED_TO_CELLS {<inst0>/u_ddr_cal_riu/mcs0 <inst1>/u_ddr_cal_riu/mcs0 <inst2>/u_ddr_cal_riu/mcs0 <inst3>/u_ddr_cal_riu/mcs0} [get_files microblaze_mcs_ddr.bmm]

If using Synplify Pro, please see (Xilinx Answer 65950).

06/29/2016 Updated for additional use cases
10/30/2015 Updated for 2015.3
07/06/2015 Initial Release

Linked Answer Records

Master Answer Records

AR# 64923
Date Created 07/06/2015
Last Updated 09/02/2016
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Virtex UltraScale
IP
  • MIG UltraScale