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AR# 64946

UltraScale RLDRAM3 - PCB pull-down required on RESET#


Version Found: RLDRAM3 v7.1

Version Resolved: See (Xilinx Answer 69037)

This Answer Record covers the UltraScale RLDRAM3 IP and is being released to alert users of our requirement to have a pull-down on RESET#.

Currently, the board guidelines documented in (UG583) UltraScale Architecture PCB Design do not include a recommendation on the RLDRAM3 RESET#.


The RLDRAM3 specification requires RESET# to be pulled LOW during power ramp.

Xilinx has not seen failures but recommends adding a pull-down to GND using a recommended 4.7KOhm resistor to meet the initialization requirement.

For customers with existing boards, the pull-down might not be required if those boards have already passed their own qualification tests.

This pull-down information will be added to (UG583) in the next revision of the document.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
69037 UltraScale/UltraScale+ RLDRAM3 - Release Notes and Known Issues N/A N/A
AR# 64946
Date 12/19/2017
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • Vivado Design Suite - 2015.2
  • MIG UltraScale
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