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AR# 64946

MIG UltraScale RLDRAM3 - PCB pull-down required on RESET#

Description

Version Found: MIG UltraScale v7.1

Version Resolved: See (Xilinx Answer 58435)

This Answer Record covers the UltraScale RLDRAM3 IP and is being released to alert users of our requirement to have a pull-down on RESET#.

Currently, the board guidelines documented in (UG583) UltraScale Architecture PCB Design do not include a recommendation on the RLDRAM3 RESET#.

Solution

The RLDRAM3 specification requires RESET# to be pulled LOW during power ramp.

Xilinx has not seen failures but recommends adding a pull-down to GND using a recommended 4.7KOhm resistor to meet the initialization requirement.

For customers with existing boards, the pull-down might not be required if those boards have already passed their own qualification tests.

This pull-down information will be added to (UG583) in the next revision of the document.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
61930 Design Advisory Master Answer Record for Virtex UltraScale FPGA N/A N/A
61598 Design Advisory Master Answer Record for Kintex UltraScale FPGA N/A N/A
AR# 64946
Date Created 07/09/2015
Last Updated 08/11/2015
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Virtex UltraScale
IP
  • MIG UltraScale