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AR# 64983

Vivado IP Integrator - How to generate a testbench for the Block Diagram (BD)


This Answer Record demonstrates how to use the testbench generator tool in the Design Utilities in the Xilinx TcL store, which provides a clock and reset stimulus.


To use this utility, go to Tools -> Xilinx Tcl Store, and select Refresh.

Once, the refresh is done. Install Design Utilities 1.17 (or later):




Open your Block Design (BD), and run the Tcl command below to generate the testbench:

tclapp::xilinx::designutils::write_ip_integrator_testbench -addToProject
AR# 64983
Date 08/28/2015
Status Active
Type General Article
  • Vivado Design Suite
  • Vivado Design Suite - 2015.2
  • Vivado Design Suite - 2015.3
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