By default, the place and route tools will automatically assign a clock root to achieve the best timing characteristics for the design.
Using the CLOCK_ROOT property lets you manually assign the clock driver, or root to a specific clock region on the target part, and hence manage clock skew.
(UG912) Vivado Design Suite Properties Reference Guide states that the applicable objects of CLOCK_ROOT can be either a global clock net or global clock buffer driving the clock net.
However, I see the following critical warning if I apply CLOCK_ROOT to a BUFGCE.
How do I correctly apply this property?
The CLOCK_ROOT property can only be assigned to the net segment driven directly by the global clock buffer.
It is illegal to attach it to a global clock buffer.
The document will be corrected in a future version.
If you want to set CLOCK_ROOT using the clock buffer name, follow the syntax example below: