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AR# 65054

UltraScale DDR4 - CAS Latency setting of 17 results in calibration failures during DQS Gate Calibration


Version Found: DDR4 v7.1

Version Resolved: See (Xilinx Answer 69035)

When CAS Latency (CL) is set to 17 for DDR4 UltraScale IP, the design will fail during calibration with DQS Gate calibration errors.

The error message is similar to the following:

Pattern not found on GT_STATUS, all samples were 0. Expecting to sample the preamble. Error found on Rank 0, Byte 0, Nibble 1.


CL=17 support has been recently added through the JEDEC JES79-4A standard.

CL=17 will be supported in a future release of DDR4 UltraScale.

Until this time, please use either 16 or 18, whichever is supported by the memory vendor.

Revision History:

07/23/2015 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
AR# 65054
Date 01/02/2018
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • Vivado Design Suite - 2015.2
  • MIG UltraScale
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