In my Partial Reconfiguration (PR) design targeting an UltraScale SSI device, there is an L-shaped PR pblock crossing the SLR boundary.
The Laguna sites in X4Y9 and X4Y8 are included into the PR pblock.
During place_design, I get the following error message:
Is this DRC error expected?
For UltraScale devices, if a PR Pblock must span an SLR, the necessary Laguna sites must be included to allow for routing across this boundary.
This requires that at least one full clock regions belongs to the PR region on both sides of the SLR boundary.
DRC (HDPR-57) should not be triggered in the design.
The issue is fixed in Vivado 2015.3.