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AR# 65057

2015.2 UltraScale Partial Reconfiguration - DRC (HDPR-57) is triggered unexpected for L-shape PR pblock crossing the SLR boundary


In my Partial Reconfiguration (PR) design targeting an UltraScale SSI device, there is an L-shaped PR pblock crossing the SLR boundary.

The Laguna sites in X4Y9 and X4Y8 are included into the PR pblock.

During place_design, I get the following error message:

ERROR: [DRC 23-20] Rule violation (HDPR-57) Reconfigurable Pblock crossing SLR using Global Clock resources - HD.RECONFIGURABLE Pblock 'pblock_XX' is not fully aligned on clock region 'X5Y8'. A reconfigurable Pblock that ranges Global Clock sources must use either an entire clock region or none of it. Because this clock region contains LAGUNA sites, the clock region above must also be included in the range. Please re-floorplan to add and use complete clock regions.

Is this DRC error expected?


For UltraScale devices, if a PR Pblock must span an SLR, the necessary Laguna sites must be included to allow for routing across this boundary.

This requires that at least one full clock regions belongs to the PR region on both sides of the SLR boundary.

DRC (HDPR-57) should not be triggered in the design.

The issue is fixed in Vivado 2015.3.

AR# 65057
Date 08/04/2015
Status Active
Type General Article
  • Vivado Design Suite - 2015.2
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