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AR# 65145

Design Advisory for Zynq-7000 PS DDR - DDR3 CKE deassertion time is too short

Description

The delay in Zynq-7000 PS DDR3 from releasing DDR_RST to asserting DDR_CKE via the reg_ddrc_pre_cke_x1024 register is too short in Vivado/EDK versions up to Vivado 2015.2, violating JEDEC specifications.

This can result in misbehavior in the DRAM device.

How do I resolve this issue?

Solution

In the Zynq-7000 PS DDR3 controller, the CKE assertion time in the reg_ddrc_pre_cke_x1024 register is counted from the assertion of reset, not the deassertion of reset, so an additional 200us must be added to the register value.

To work around this issue, edit the DRAM_BURST8_RDWR.reg_ddrc_pre_cke_x1024(0XF8006034[13:4]) register in the ps7_init.c and ps7_init.tcl files.

 

The resulting decimal value of reg_ddrc_pre_cke_x1024 multiplied by 1024 and the DDR clock period should equal 700us (200us reset time + 500us CKE delay after reset deassertion).

DDR2 and LPDDR2 are unaffected.

 

This issue is fixed starting with Vivado 2015.3.

EDK XPS will not be updated, the work-around must be used.

AR# 65145
Date Created 08/05/2015
Last Updated 10/16/2015
Status Active
Type Design Advisory
Devices
  • XA Zynq-7000
  • Zynq-7000
  • Zynq-7000Q
Tools
  • EDK - 14.7
  • Vivado Design Suite - 2015.2
  • Vivado Design Suite - 2015.1
  • More
  • Vivado Design Suite - 2014.4.1
  • Vivado Design Suite - 2014.4
  • Less
IP
  • Processing System 7