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AR# 65171

Design Advisory for AXI QUAD IP for 7 Series FPGA - How to constrain the input/output QSPI interface in post-configuration mode with a STARTUPE2 primitive?


Are there any guidelines on constraining the Flash SCK signal with respect to data signals?

PG153, does explain the timing constraints but there is no explanation of how and why this is done.

Can you provide more information on the timing waveform for the QSPI with respect to AXI QSPI IP access?

How do I constrain the STARTUPE2 primitive with respect to SCK and the MOSI and MISO signals?


Limitation on operating frequency of AXI QSPI when STARTUP block is enabled

The frequency of operation of AXI-QSPI is affected when a STARTUP primitive is enabled. 

The STARTUP primitive is used to drive the SCK on the CCLK pin. 

This primitive has its own delay which is not accounted for anywhere in the entire implementation/timing process. 

The tool does not take into account the delay added due to the presence of the STARTUP primitive in the design. 

This article will enable the user to understand the limitations which are introduced due to the presence of the STARTUP block.

Clock relationships when SCK ratio is 2: 

(QUAD and DUAL MODE Selection only. SCK ration divide by 2 does not work for Standard SPIx1 mode)

The above waveform shows the ideal clock data relationship. 

The IP drives data on every alternate rising edge of ext_spi_clk which is captured into the SPI device on the rising_edge of SCK. 

The SPI device drives the data on the falling edge of SCK which is captured into the FPGA on the second rising_edge. 

When we use the STARTUP primitive, the clock-data relationship changes due to the extra delay added in the SCK path. 

This delay can vary from as low as 0.5ns to as high as 7.5ns based on the device and speed grade. 

This value can be found in the FPGA datasheet.

Since this delay is not timed by the tool, we have to consider the Max delay for all calculations. 

Let us call this delay CCLK_DELAY. For K7-2 this value can range from 0.5ns to 6.7ns. 

This puts the first restriction on the frequency of the clock.

The frequency of operation cannot exceed Fmax1 = (1/CCLK_DELAY) Mhz

Write operation to SPI:

A successful write operation should be completed within 2 clock cycles of ext_spi_clk. 

This means:

  • The rising_edge of SCK must be between these two active edges of ext_spi_clk

  • The position of the rising_edge of SCK should be such that it meets the Tsetup and Thold time of the SPI device.

  • Tsetup analysis should be done by taking into account the min delay on SCK (i.e. the min delay of STARTUP), the max delay of the data path and the board routing delay

  • Similarly Thold analysis should be done by taking into account the max delay on SCK (i.e. the max delay of STARTUP), the min delay of data and the board routing delay

This requirement of the SPI device further brings down the operational frequency of the IP. 

Based on this we get two numbers. Fmax that will break Tsu and Fmax that will break Th:

Fmax2 = fn {STARTUP delay min, max data path, board routing delay, Tsu}

Fmax3 = fn {STARTUP delay max, min data path, board routing delay, Th}

The more restrictive number of the above two has to be considered.

Read Operation:

A successful read operation occurs when the SPI data, launched on the falling_edge of SCK, is captured on the 2nd rising_edge of ext_spi_clk.

This means:

Data should be available and stable at the time the capture happens on the 2nd rising_edge.

The worst case scenario would be when:

  • SCK has max delay on the line (i.e. Max delay of STARTUP)
  • SPI drives the data with max Tco

Fmax4 = fn {STARTUP delay max, Tco-max, board routing}

Thus the actual Fmax is the one that is most restrictive amongst Fmax2, Fmax3 and Fmax4.

Constraining the IP:

To understand how the constraints are added, it is important to understand the logic structure around clock and data in AXI QSPI.

The following figure gives an idea of the logic structure:

The STARTUP primitive adds delay on the USRCCLKO to CCLK pin. 

This delay is unaccounted for in the tool and is not considered in the timing calculation. For the tool, the timing path ends at USRCCLKO.

In order to come up with the required constraints we need to somehow take into account the delay of STARTUP primitive.

As the timing path ends at USRCCLKO, we cannot create a clock on the CCLK pin.

In order to emulate the SCK clock, we have to create a generated clock such that the STARTUP primitive delay is taken into account

This can be achieved by creating a generated clock on the USRCCLKO pin.

This would take into account the delay of the Flop that generates the SCK, the routing delay from that Flop to USRCCLKO pin and the STARTUP primitive delay. 

Further, in order to reduce the delay on SCK we have to ensure that the delay from Flop to USRCCLKO is as low as possible. 

This can be constrained by using set_max_delay. 

The data paths can then be constrained using set_output_delay and set_input_delay along with set_multicyle_path constraints.

Constraints Explanation for 7 series FPGA:

(Note: The below example is based on a KC705)

The following XDC constraints can be used to time AXI QSPI when a STARTUP primitive is used:

# All the delay numbers have to be provided by the user
# CCLK delay is 0.5, 6.7 ns min/max for K7-2; refer to the Datasheet (DS182.page.64.Table 71: Configuration Switching Characteristics)
# We need to consider the max delay for worst case analysis
set cclk_delay 6.7
# Following are the SPI device parameters
# Max Tco
set tco_max 7
# Min Tco
set tco_min 1
# Setup time requirement
set tsu 2
# Hold time requirement
set th 3
# Following are the board/trace delay numbers
# Assumption is that all Data lines are matched
set tdata_trace_delay_max 0.25
set tdata_trace_delay_min 0.25
set tclk_trace_delay_max 0.2
set tclk_trace_delay_min 0.2
### End of user provided delay numbers
# This is to ensure min routing delay from SCK generation to STARTUP input
# User should change this value based on the results
# Having more delay on this net reduces the Fmax
# Following constraint should be commented when the STARTUP block is disabled
set_max_delay 1.5 -from [get_pins -hier *SCK_O_reg_reg/C] -to [get_pins -hier *USRCCLKO] -datapath_only
set_min_delay 0.1 -from [get_pins -hier *SCK_O_reg_reg/C] -to [get_pins -hier *USRCCLKO]
# Following command creates a divide by 2 clock
# It also takes into account the delay added by the STARTUP block to route the CCLK
# This constraint is not needed when the STARTUP block is disabled
# The following constraint should be commented when the STARTUP block is disabled
create_generated_clock -name clk_sck -source [get_pins -hierarchical *axi_quad_spi_1/ext_spi_clk] [get_pins -hierarchical *USRCCLKO] -edges {3 5 7} -edge_shift [list $cclk_delay $cclk_delay $cclk_delay]
# Enable the following constraint when STARTUP block is disabled
#create_generated_clock -name clk_virt -source [get_pins -hierarchical *axi_quad_spi_1/ext_spi_clk] [get_ports <SCK_IO>] -edges {3 5 7}
# Data is captured into FPGA on the second rising edge of ext_spi_clk after the SCK falling edge
# Data is driven by the FPGA on every alternate rising_edge of ext_spi_clk
set_input_delay -clock clk_sck -max [expr $tco_max + $tdata_trace_delay_max + $tclk_trace_delay_max] [get_ports IO*_IO] -clock_fall;
set_input_delay -clock clk_sck -min [expr $tco_min + $tdata_trace_delay_min + $tclk_trace_delay_min] [get_ports IO*_IO] -clock_fall;
set_multicycle_path 2 -setup -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]]
set_multicycle_path 1 -hold -end -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]]
# Data is captured into SPI on the following rising edge of SCK
# Data is driven by the IP on alternate rising_edge of the ext_spi_clk
set_output_delay -clock clk_sck -max [expr $tsu + $tdata_trace_delay_max - $tclk_trace_delay_min] [get_ports IO*_IO];
set_output_delay -clock clk_sck -min [expr $tdata_trace_delay_min -$th - $tclk_trace_delay_max] [get_ports IO*_IO];
set_multicycle_path 2 -setup -start -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck
set_multicycle_path 1 -hold -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck

For more information, please see the attached QSPI_Fmax.xlsx Excel spreadsheet.


Associated Attachments

Name File Size File Type
QSPI_AR_Design_advisory_QSPI_FMAX.xlsx 18 KB XLSX
AR# 65171
Date 08/12/2015
Status Active
Type Design Advisory
  • Artix-7
  • Artix-7Q
  • Kintex-7
  • More
  • Kintex-7Q
  • Virtex-7
  • Virtex-7Q
  • Zynq-7000
  • XA Zynq-7000
  • Zynq-7000Q
  • Less
  • Vivado Design Suite
  • AXI Serial Peripheral Interface
Boards & Kits
  • Kintex-7 Boards and Kits
  • Virtex-7 Boards and Kits
  • Artix-7 Boards and Kits
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