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AR# 65178

Virtex-6 FPGA Integrated Block for PCI Express - Master Answer Record

Description

This master answer record for Virtex-6 FPGA Integrated Block for PCI Express core lists all release notes, Design Advisories, known issues and general information answer records for different versions of the core.

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This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536) Xilinx Solution Center for PCI Express

Solution

Release Notes:

(Xilinx Answer 32742) Release Notes v1.2 and v1.2.1
(Xilinx Answer 33276) Release Notes v1.3, v1.3 rev2
(Xilinx Answer 33763) Release Notes v1.4
(Xilinx Answer 35322) Release Notes v1.5
(Xilinx Answer 37936) Release Notes v1.6
(Xilinx Answer 40446) Release Notes v1.7
(Xilinx Answer 37937) Release Notes v2.1
(Xilinx Answer 39353) Release Notes v2.2
(Xilinx Answer 40445) Release Notes v2.3
(Xilinx Answer 42756) Release Notes v2.4
(Xilinx Answer 45723) Release Notes v2.5

Design Advisories:

(Xilinx Answer 37042) Design Assistant for PCI Express - Is 128-bit interface maintained when x8 Gen2 comes up in Gen1 speed?
(Xilinx Answer 37207) Design Advisory for the Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - x8 Gen 2 128-bit Wrapper is Not Deasserting trn_tdst_rdy_n When Integrated Block Transmit Buffer is Full
(Xilinx Answer 33775) Design Advisory Master Answer Record for the Virtex-6 FPGA Integrated Block Wrapper for PCI Express
(Xilinx Answer 34260) Design Assistant for PCI Express - trn_terr_drop_n Asserted when Transmitting a Valid Packet
(Xilinx Answer 39164) Design Advisory for the Virtex-6 Integrated Block for PCI Express - Need to set BANDWIDTH attribute on MMCM to Low
(Xilinx Answer 39397) Design Assistant for PCI Express, Virtex-6 Integrated Block for PCI Express - Does Virtex-6 CXT FPGA support PCI Express Gen2?
(Xilinx Answer 39456) Design Advisory for the Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Delay Aligner Workaround
(Xilinx Answer 39488) Design Assistant for PCI Express - Virtex-6 Integrated Block for PCI Express ChipScope Pro Templates
(Xilinx Answer 45771) Design Advisory for the Virtex-6 Integrated Block for PCI Express - The receive interface signal m_axis_rx_tvalid might deassert in the middle of a packet when using the 128-bit x8 Gen 2 interface


Known Issues/General Information:

(Xilinx Answer 33042) Virtex-6 Integrated Block Wrapper v1.2 for PCI Express - Patch updates for the Virtex-6 Integrated Block for PCI Express
(Xilinx Answer 33046) Virtex-6 Integrated Block Wrapper v1.2 for PCI Express - In x8 Gen 2 Mode, TLP May be Dropped on Transmit Interface when Buffers are Full
(Xilinx Answer 33127) Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - UCF constraint for sys_clk incorrect for ML605
(Xilinx Answer 33946) Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Missing UCF constraint for x1, x2, and x4 Gen1 designs with a User Interface Clock of 250 MHz
(Xilinx Answer 34279) Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Patches and Wrapper Source Code Updates
(Xilinx Answer 34280) Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Gen 1 Training Fails with 100 MHz reference clock
(Xilinx Answer 34612) Virtex-6 FPGA Integrated Endpoint Block v1.4 for PCI Express : Simulation failure when using ISE 11.5 to simulate a v1.4 core generated in ISE Design Suite 11.4
(Xilinx Answer 35422) Virtex-6 FPGA Integrated Block Wrapper for PCI Express - v1.3 Rev 1 Patch for ISE Design Suite 12.1
(Xilinx Answer 35426) Virtex-6 FPGA Integrated Block for PCI Express - The v1.3, v1.3 rev 1, v1.4, and v1.4 rev 2 wrapper might not link train on startup when using ISE Design Suite 11.5 or later
(Xilinx Answer 36008) Virtex-6 FPGA Integrated Block Wrapper for PCI Express - The v1.3 and v1.3 rev 1 Core is not linking up reliably on ES (engineering sample) silicon using ISE 12.1 and ISE 11.5 or later software
(Xilinx Answer 36019) Virtex-6 FPGA Integrated Block for PCI Express - Coregen allows generating a x8 Gen 2 design for the XC6VLX550T-2; But this is not supported
(Xilinx Answer 36545) Virtex-6 FPGA Integrated Block Wrapper PCI Express - Core never link trains when upper lanes are intentionally not used
(Xilinx Answer 36552) Virtex-6 FPGA Integrated Block Wrapper v1.3 for PCI Express - v1.3 Rev 2 Patch for ISE Design Suite 12.1
(Xilinx Answer 36677) Virtex-6 FPGA Integrated Block Wrapper v1.3 rev 2 and v1.5 for PCI Express - Updated MGT Settings
(Xilinx Answer 37784) Virtex-6 FPGA Integrated Block for PCI Express - x8 Gen 2 Timing Closure
(Xilinx Answer 37963) Virtex-6 FPGA Integrated Block for PCI Express - VHDL Wrapper Not Available for v2.1 Release
(Xilinx Answer 38223) Virtex-6 Integrated Block for PCI Express - Disabling Legacy Interrupts in the GUI does not change Interrupt Pin register
(Xilinx Answer 38848) Virtex-6 Integrated Block Wrapper v1.6 for PCI Express - Corrections for UG517
(Xilinx Answer 40637) Virtex-6 FPGA Integrated Block for PCI Express - DRC Error During Simulation using Provided Root Port Model
(Xilinx Answer 41051) Virtex-6 FPGA Integrated Block for PCI Express - x8 Gen 2 128-bit Transmit Interface May Drop Single Cycle Packets
(Xilinx Answer 42123) Virtex-6 FPGA Integrated Block Wrapper v1.7 for PCI Express - Linkup failure in Simulation with PIPERXVALID going undefined
(Xilinx Answer 43531) Virtex-6 FPGA Integrated Block for PCI Express - When I simulate a VHDL x8 Root Port, the example design does not link up until around 122 microseconds
(Xilinx Answer 46793) Virtex-6 Integrated Block for PCI Express v2.5 - Timing constraints for x8 gen2 with a 250Mhz refclk are incorrect
(Xilinx Answer 57345) Virtex-6 Integrated Block for PCI Express v2.5 - Bus/Device/Function Number Change Upon Configuration Type 1 Accesses Article


AR# 65178
Date Created 08/10/2015
Last Updated 01/28/2016
Status Active
Type General Article
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )