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AR# 65226

How to connect multiple slave peripheral interrupts to AXI_INTC IP in IP Integrator?


I have a MicroBlaze based IPI block design in which I have included some AXI slave peripherals like UART lite, IIC, QSPI and GPIO.

I want to connect the interrupts of the slave peripherals to the newly added interrupt controller IP (axi_intc) but the IPI drag and connect pencil is not allowing me to do it.

How do I make these interrupt connections to AXI INTC IP?


You will need to add additional IP called Concat to the block diagram. The Concat IP will concatenate the individual interrupt signals into the bus.

This IP is a general purpose block to combine multiple inputs into single bus outputs.

The individual interrupt signals from AXI slave IP cores need to be connected to the Concat IP input. 

Concat will combine the interrupt signals into a bus output connecting to the interrupt controller which takes a bus as its input.

Steps to do this in IP Integrator:

1) Right-click on the design canvas to open the pop-up menu and select Add IP.

2) Type "concat" in the search field to find the Concat block. 

Double click on the core to add.

3) Double-click on the Concat IP to open the Re-customize IP dialog box.

4) Edit the Number of Ports to match the number of interrupts which will be connected to the Concat IP, and change the width of the interrupt signals if required.

The ports are needed to connect the interrupt pins on the various slave IP blocks into the Interrupt Controller.

5) Next, connect the interrupt signals of the AXI slaves to the Concat block to create an interrupt bus. Hover the cursor on top of the interrupt pin of the AXI slave peripherals.

Notice that the cursor changes into a pencil indicating that a connection can be made from that pin.

6) Click and drag pencil to make connections from the interrupt port to an input port on the Concat block, as shown in the following example:

7) Make the connections from the Concat bus output to the AXI interrupt controller interrupt input port.

8) Note that the 1-bit bus width of the interrupt signal on the Interrupt Controller block does not match the number of the interrupt bits signal width from the Concat block. 

This is automatically corrected during design validation.

AR# 65226
Date 11/26/2015
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Vivado Design Suite - 2015.2
  • Vivado Design Suite - 2015.1
  • Vivado Design Suite - 2014.4
  • AXI Interrupt Controller
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