This answer record contains the Release Notes and Known Issues for the MIPI CSI-2 Receiver Subsystem and includes the following:
IP MIPI CSI-2 Receiver Subsystem Page:
Supported Devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.
This table correlates the core version to the first Vivado design tools release version in which it was included.
Table 1: Version
|Core Version||Vivado Tools Version|
|v2.2 (Rev. 1)||2017.2|
|v2.1 (Rev. 1)||2016.4|
|v2.0 (Rev. 1)||2016.2|
The table below provides Answer Records for general guidance when using the MIPI CSI-2 Receiver Subsystem.
Table 2: General Guidance
|Article Number||Article Title|
|(Xilinx Answer 69322)||Why do I get Vivado implementation errors after changing the Calibration Mode to Auto?|
Known and Resolved Issues
The following table provides known issues for the MIPI CSI-2 Receiver Subsystem , starting with v1.0, initially released in Vivado 2015.3.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
Table 3: IP
|Article Number||Article Title||Version Found||Version Resolved|
|(Xilinx Answer 69441)||Why is the MIPI CSI-2 Receiver with Clock/Data skew calibration set to Auto/Fixed, failing during implementation?||v2.1 (Rev. 1)||N/A|
|(Xilinx Answer 69057)||Why is an SOTsynchs error generated from MIPI DPHY RX IP or MIPI CSI-2 Rx Subsystem?||v2.1 (Rev. 1)||v2.2|
|(Xilinx Answer 67960)||Why do I get a Critical Warning (Vivado 12-1433) when implementing the IP in OOC mode in the Vivado IDE?||v2.1||N/A|
|(Xilinx Answer 67793)||Why do I see timing failing on the video_aresetn when using two CSI-2 Receiver Subsystems with one as a master and one as a slave?||v2.0 (Rev. 1)||v2.1|
|(Xilinx Answer 66994)||Why do I get a CRITICAL WARNING about 'vfb_v1_0_2_viv_fifo_gen.v' when instantiating multiple MIPI CSI-2 Receiver Subsystems on my design?||v2.0||v2.0 (Rev. 1)|
|(Xilinx Answer 65741)||Why do I see [Designutils 20-1280] when opening a design in the Vivado elaboration mode?||v1.0||v2.0|
|07/07/2017||Added (Xilinx Answer 69441).|
|06/20/2017||Added v2.2 (Rev.1) to Version Table and (Xilinx Answer 69322).|
|04/05/2017||Added v2.1 (Rev.1) and v2.2 to Version Table and (Xilinx Answer 69057).|
|10/05/2016||Added v2.0 (Rev.1) and v2.1 to Version Table, (Xilinx Answer 67793) and (Xilinx Answer 67960) .|
|04/06/2016||Added v2.0 to Version Table and Added (Xilinx Answer 66994).|
|10/20/2015||Added (Xilinx Answer 65741)|