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AR# 65263

Virtex UltraScale FPGA VCU108 Evaluation Kit - 2015.3 / 2015.4 - DDR4 SDRAM interface usage

Description

This Answer Record provides details on using the DDR4 SDRAM interfaces on the Virtex UltraScale FPGA VCU108 Evaluation Kit.

Solution

The VCU108 has 2 DDR4 SDRAMs (C1 and C2) available on board. These can be used in three modes.

  • C1 individually [C1 mode]
  • C2 individually [C2 mode]
  • C1 and C2 in a single project [C1+C2 mode]

C1 is connected to banks 49, 50 and 51.
C2 is connected to banks 44, 45, 46.

The 300 MHz system clock connected in Bank 50 can be connected to both of these components.
To connect the clock to C2, an IBUFDS followed by a BUFG is needed, which will drive the sys_clk for DDR4 IP.

Using DDR4 IP in IPI

To build an IPI system in any of the three modes listed above:

1) Add util_ds_buf IP to IPI and, with designer assistance, connect input clock interface "CLK_IN_D" to the "default_sysclk1_300" clock interface.


 

The above Screen capture shows an instantiated IBUFDS, which is needed in all three modes.


2) Specific instructions for each mode can be found below:


[C1 mode] - Using DDR4_SDRAM_C1

  • Drag and Drop the interface DDR4_SDRAM_C1 interface from the Board Tab
  • The output of the util_ds_buf_0 IP is connected to the 'c0_sys_clk_i' pin of the DDR4_0 IP
  • With designer assistance, connect the sys_rst interface of the ddr4_0 IP to the "reset" interface
  • Add c1.xdc to the project

Using DDR4_SDRAM_C1:


 

[C2 Mode] - Using DDR4_SDRAM_C2


  • Drag and Drop the DDR4_SDRAM_C2 interface from the Board Tab
  • Add a second UTIL_DS_BUF IP(xilinx.com:ip:util_ds_buf) and customize the IP:
    • Leave the board interface for DIFF_CLK_IN as custom in the Board page
    • On the next page Set C_BUF_TYPE to 'BUFG'
  • The output of util_ds_buf_0 is connected to the BUFG_I pin of the BUFG (util_ds_buf_1)
  • Connect the output BUFG_O pin of BUFG (util_ds_buf_1) to the 'c0_sys_clk_i' pin of the DDR4_0 IP
  • With designer assistance, connect the sys_rst interface of the ddr4_0 IP to the "reset" interface
  • Add c2.xdc to the project

Using DDR4_SDRAM_C2:




[C1+C2 mode] - Using DDR4_SDRAM_C1 + DDR4_SDRAM_C2

  • Drag and Drop the DDR4_SDRAM_C1 and DDR4_SDRAM_C2 interfaces from the Board Tab
  • Add another UTIL_DS_BUF IP(xilinx.com:ip:util_ds_buf) and configure it so that C_BUF_TYPE is set to 'BUFG'
  • Connect the output of IBUFDS (util_ds_buf_0) to
    • 'The c0_sys_clk_i' pin of the DDR4_0 IP
    • The 'BUFG_I' pin of the BUFG (util_ds_buf_1)
  • Connect the output BUFG_O pin of BUFG (util_ds_buf_1) to the 'c0_sys_clk_i' pin of the DDR4_1 IP
  • With designer assistance, connect the sys_rst interface of the ddr4_0 and ddr4_1 IPs to the "reset" interface
  • Add c1_c2.xdc to the project

Using DDR4_SDRAM_C1 + DDR4_SDRAM_C2:




Using DDR4 from IP Catalog

To use DDR4 IP in standalone or non-IPI mode, the following procedure applies:

  • Customize the DDR4 IP from IP catalog and select the board interfaces:
    • C0_SYS_CLK should be set to Custom
    • DDR4 interface: ddr4_sdram_c1 or ddr4_sdram_c2 as needed
    • SYSTEM_RESET: reset




  • Open the IP example design for the IP generated.
  • For a C1 interface, add native_c1.xdc to the project as constraints.
  • For C2:
    • The file example_desgin.sv needs to be modified as shown below to drive the system clock input of the DDR4 IP from the IBUFDS through the BUFG.



    • Add native_c2.xdc to the project as constraints.
  • The Example design now runs through the Vivado flow.

Attachments

Associated Attachments

Name File Size File Type
c1.xdc 64 Bytes XDC
c2.xdc 204 Bytes XDC
c1_c2.xdc 204 Bytes XDC
native_c1.xdc 618 Bytes XDC
native_c2.xdc 767 Bytes XDC

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
62603 Virtex UltraScale FPGA VCU108 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A
AR# 65263
Date Created 08/20/2015
Last Updated 08/05/2016
Status Active
Type Design Advisory
Devices
  • Virtex UltraScale
Tools
  • Vivado Design Suite - 2015.3
  • Vivado Design Suite - 2015.4
IP
  • MIG UltraScale
Boards & Kits
  • Virtex UltraScale FPGA VCU108 Evaluation Kit