We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 65331

MIG (7 Series) - Generated clocks unconnected to clock source severe warning in Check Timing


Version Found: MIG 7 Series v2.3 Rev2

Version Resolved: See (Xilinx Answer 54025)

When reviewing the Check Timing Summary for the 7 Series DDR3 MIG core, I see the following Critical Warning.

Why does this occur?

Can it be safely ignored?


This occurs because the CLKOUT4 output from the PLLE2 instantiated in the MIG RTL is connected to a BUFH, but the BUFH output is not connected to anything within the MIG and is not available at the MIG top level either.

This is not required for a MIG core and it can be safely ignored.

The Vivado software tools should optimize this connection away in the implemented design. 

If that does not occur, it is safe to manually modify the MIG code to remove this BUFH. 

However, if the MIG core is regenerated it will overwrite any modification made unless the MIG has the "IS_MANAGED" property disabled.

See (Xilinx Answer 57546) for information on modifying the RTL.

Revision History

25/09/2015 - Initial Release

AR# 65331
Date 10/20/2015
Status Active
Type Known Issues
  • Vivado Design Suite - 2015.1
  • Vivado Design Suite - 2015.2
  • Vivado Design Suite - 2015.3
  • More
  • Vivado Design Suite - 2014.4.1
  • Vivado Design Suite - 2014.4
  • Vivado Design Suite - 2014.3
  • Less
  • MIG 7 Series
Page Bookmarked