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AR# 65345

G.709 FEC Encoder/Decoder​ Behavioral simulation fails with an assertion error - Error: sts count exceeded maximum sts count

Description

This is a known issues article for the G.709 FEC Encoder/Decoder.

When the G.709 FEC Encoder/Decoder is configured to have an AXI interface and no statistics reference design, the m_axis_dsts_tready signal may be used to throttle the output of the DSTS packet, in line with the AXI-4 Stream protocol.

A new DSTS packet is output by the decoder for every frame.

If m_axis_dsts_tready is de-asserted when the DSTS packet is ready to be output, the packet is lost (as described in (PG024), "Decoder Status Interface").

If m_axis_dsts_tready is de-asserted for more than three output frames, behavioral simulation fails with an assertion error.

No such assertion is triggered during post-synthesis simulations, however the resulting behavior of the DSTS channel might be incorrect.

Solution

This is a known issue with G.709 FEC v2.2.

Xilinx recommends that the m_axis_dsts_tready pin be tied High for all configurations, and any delayed reading of the DSTS packets be managed by using a FIFO external to the core.


Note: The "Version Found" column lists the version the problem was first discovered.

The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions.

Linked Answer Records

Master Answer Records

AR# 65345
Date Created 09/05/2015
Last Updated 09/09/2015
Status Active
Type Known Issues
Devices
  • FPGA Device Families
Tools
  • Vivado Design Suite