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AR# 65346

LogiCORE IP G.709 FEC Encoder/Decoder v2.1/2.2 - Timing violation when SP48E2 XOR features are used in Virtex-7 and UltraScale Virtex Devices

Description

It might not be possible to achieve timing closure for Virtex-7 and Virtex UltraScale devices if you are using an encoder and ENCODE_DSP is set to anything other than LUT_BIAS.

Solution

To work around this issue, set ENCODE_DSP to LUT_BIAS.

This is functionally equivalent.

AR# 65346
Date Created 09/06/2015
Last Updated 09/09/2015
Status Active
Type General Article
Devices
  • Virtex-7
  • Virtex UltraScale
Tools
  • Vivado Design Suite