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AR# 65370

UltraScale/UltraScale+ Memory IP - pblocks containing Memory IP logic must be contained within the same clock region the memory I/O is located in


Version Found: DDR4/DDR3/RLDRAM3/QDRII+/QDRIV v1.0

Version Resolved: See (Xilinx Answer 58435)

In the 2015.3 release, pblock constraints for UltraScale Memory IP will be generated by the Vivado Placer during place_design.

These pblock constraints created by the Vivado Placer are hidden and not visible to the user. 

However, if you add your own pblock constraints that include the UltraScale Memory IP, then the Vivado Placer will not generate the hidden pblock constraints, which could lead to timing issues.


In order to prevent timing issues, any user created pblocks that contain UltraScale Memory IP must be contained within the same clock region as the memory I/O. 

Because the pblocks need to be constrained to the same region as the memory I/O, it is recommended to place the I/O and create the pblock in the post-synthesis DCP.

The following procedure can be followed to do this:

  1. Open Synthesized DCP
  2. Open I/O Planner
  3. Place all memory I/O
  4. Open Device View
  5. Select the MIG module
  6. Right click and select Floorplanning => Draw Pblock
  7. Uncheck DSP48 (and RAMB18/RAMB36 if single bank memory interface)
  8. Draw the Pblock, provide the name, click OK.

Note: Make sure pblock is contained in the same clock region as the memory I/O.

Revision History:

09/30/2015 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 UltraScale/UltraScale+ Memory IP - Master Release Notes and Known Issues N/A N/A
AR# 65370
Date 01/12/2018
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • Kintex UltraScale+
  • More
  • Virtex UltraScale+
  • Zynq UltraScale+ MPSoC
  • Less
  • MIG UltraScale
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