When I try to load a design for Verilog simulation, the following error occurs:
"ERROR: ../<project>/<module.v>: Unresolved reference to 'glbl' in 'glbl.GSR'"
This error occurs because the glbl.v module is not used during compilation and loading of the design. The glbl.v module is required for the global set/reset in the design, and it is referenced by the UniSim and the SimPrim libraries.
Please refer to (Xilinx Answer 6537) for information on how to use the glbl.v module in Verilog simulations.
An example of the syntax used is:
vsim -t 1ps -L unisims_ver work.glbl work.tb
In the example above, glbl.v is loaded at the same time as the testbench (which is called "tb" in this instance).