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AR# 65385

Vivado Logic Debug - Error complains that there are multiple debug hubs in the design when opening a synthesized design


When I open synthesized design I see the below error:

[Common 17-70] Application Exception: This design contains multiple debug hubs and must be re-synthesized; it cannot be upgraded to work with the latest debug hub core.

Rerunning synthesis does not help.

If I disable OOC synthesis on the block designs then the error does not appear.


You can work around this issue by doing the following:

  1. Do not use OOC modules in this situation
  2. Remove the MIG IP from the OOC module and instantiate the two required MIGs directly in the top level, connecting them to the two instantiated OOC modules
AR# 65385
Date 11/05/2015
Status Active
Type General Article
  • FPGA Device Families
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