When I apply procedure "print " in VHDL within a pure function, I get the following synthesis error: [Synth 8-1730].
Error message in Vivado 2014.3:
How can I resolve this issue?
To work around this issue, avoid using the procedure "print" in VHDL within a pure function.
In Vivado 2015.3, the error message is changed to a Warning similar to the following: