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# AR# 65408

## Description

I get the following information in my timing report for an intra-clock path in the design:

Clock Path Skew: -0.679ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.568ns = ( 12.568 - 10.000 )
Source Clock Delay (SCD): 3.929ns
Clock Pessimism Removal (CPR): 0.682ns
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.129ns
Phase Error (PE): 0.000ns
Clock Net Delay (Source): 3.056ns (routing 1.011ns, distribution 2.045ns)
Clock Net Delay (Destination): 2.295ns (routing 0.926ns, distribution 1.369ns)

The conservative common code of the clock path is the clock root of BUFGCE net.

So the clock skew = Distribution(Destination) 1.369 ns - Distribution(Source) 2.045 ns = -0.676 ns

The current reported clock path Skew is -0.679 ns < -0.676 ns.

Why does this discrepancy occur?

## Solution

In some cases the reported routing and distribution delays of clock net are inaccurate in Vivado 2015.3, but the slack the timing path is not affected.

In Vivado 2016.1, the issue is fixed and the correct report is similar to the following:

Clock Path Skew:        -0.679ns (DCD - SCD + CPR)
Destination Clock Delay (DCD):    2.568ns = ( 12.568 - 10.000 )
Source Clock Delay      (SCD):    3.929ns
Clock Pessimism Removal (CPR):    0.682ns
Clock Uncertainty:      0.074ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter     (TSJ):    0.071ns
Discrete Jitter          (DJ):    0.129ns
Phase Error              (PE):    0.000ns
Clock Net Delay (Source):      3.056ns (routing 0.979ns, distribution 2.077ns)
Clock Net Delay (Destination): 2.295ns (routing 0.897ns, distribution 1.398ns)

In this report, the clock skew calculated from the Clock Net distribution delays matches the Clock Path Skew reported: 1.398-2.077 = -0.679.

AR# 65408
Date 10/06/2015
Status Active
Type General Article
Devices
• Kintex UltraScale
Tools
• Vivado Design Suite - 2015.3
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