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AR# 65409

Vivado Synthesis - "[Synth 8-658] type mismatch for port" Port mapping with VHDL alias results in Vivado Synthesis error

Description

I have the following port mapping definition in my design:

-----------------------------------------
Memory Declaration
-----------------------------------------
type ram_test is array (1 downto 0) of std_logic_vector(31 downto 0);
signal memory : ram_test;
-----------------------------------------
Alias Declaration
-----------------------------------------
alias to_portmap : std_logic_vector(7 downto 0) is memory(0)(7 downto 0);
-----------------------------------------
Port Map
-----------------------------------------
sub_module
    port map (
  .........
        offset_1   => to_portmap(4 downto 0),
        clk       => clk,
  .........
     
    ); 

Vivado is generating the below error message in the synthesis phase:

[Synth 8-658] type mismatch for port 'offset_1' 

Solution

To work around the issue, make the change below:

sub_module
    port map ( 
  .........
        offset_1   => memory(0)(4 downto 0),
        clk       => clk,
  .........
     
    ); 

After you modify the definition of the port map, the design will be able to complete the synthesis.

AR# 65409
Date 04/19/2017
Status Active
Type Known Issues
Tools
  • Vivado Design Suite