Please refer to this Answer Record for help with Register Balancing.
Register balancing or Retiming enables a flip-flop retiming algorithm in the Vivado synthesis process.
Retiming will improve the design timing performance by moving flip-flops and latches across the logic to increase clock frequency.
Starting with Vivado 2015.3, retiming can be enabled in Vivado synthesis using the following Tcl command:
set_param synth.elaboration.rodinMoreOptions "rt::set_parameter synRetiming true"
Starting from Vivado 2016.1, a new option "-retiming" is added into Synthesis settings and synth_design command as a formal support of retiming.