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AR# 65413

Vivado Synthesis: RLOC and BEL attributes not supported when accessing array of strings

Description

Synthesized netlists do not have RLOC and BEL properties for the below RTL usage:


 genvar g; 
   generate
      for (g=0; g < n; g++) begin: regs
        localparam rlocpre = "X0Y";
        localparam byte rlocbyte = g/n + m;
        localparam rloc = {rlocpre,rlocbyte};  
         localparam bel[8] = {"AFF", "A5FF", "BFF", "B5FF", "CFF","C5FF", "DFF", "D5FF"};
    (* RLOC = rloc, BEL = bel[g%n] *) FDRE u(.C(clk), .D(d[g]), .Q(q[g]), .CE(1'b1), .R(1'b0)); end
endgenerate


The properties can be checked after loading the design or by writing an EDIF file.

Solution

Vivado Synthesis does not support RLOC and BEL usage in an array of string format.

To work around this issue, modify the RTL description to avoid array of string usage.

AR# 65413
Date Created 09/15/2015
Last Updated 09/23/2016
Status Active
Type Known Issues
Tools
  • Vivado Design Suite