AR# 65415


Vivado Synthesis - VHDL Assertion Support


Are VHDL assertions supported in Vivado?

For example:

assert <condition> report <message_string> severity <severitylevel>;


VHDL assertions are supported in Vivado 2015.3, but can only be enabled with the following Tcl switch:

set_param synth.elaboration.rodinMoreOptions {rt::set_parameter ignoreVhdlAssertStmts false}

Starting with Vivado 2016.1, this support is documented and replaced with an -assert switch in synth_design.

Prior to 2015.1, Vivado Synthesis could not correctly catch all asserts in a design.

In Vivado Synthesis 2015.1 and 2015.2, a warning is given stating that it will not process the assert statements.

The warning about not processing asserts will still be issued in Vivado 2015.3, but the Tcl switch will now catch asserts and issue an error if the assert is true and its severity is set to "failure".

AR# 65415
Date 04/13/2016
Status Active
Type General Article
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