When synthesizing a design with several hierarchies, much of the logic is optimized after opt_design.
There can be a disconnect between hierarchies, caused by the wrong direction being assigned in on of the RTL files. However, Vivado Synthesis does not report a warning about this issue.
In the following example, a Verilog port which should have been defined as an output, was mistakenly set as an input.
This caused the net within this module to have two drivers, but no output.
Also, this output was supposed to drive other logic in another hierarchy which eventually was optimized away.
There is no plan to provide an error message for this situation.
Even though the direction and inferred connection were not expected, this is still legal syntax in Verilog.
To work around this issue, trace the opt_design trimming by enabling the -verbose option, to find the root cause of similar connection issues.