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AR# 65419

Vivado Synthesis - Long Runtime for RAM Initialization Code


Vivado 2014.x and 2015.x seems to hang/have a long runtime during the Elaboration stage.

A number of existing designs that used to work under ISE no longer work under Vivado.

The problem seems to be related to RAM initialization.

Can Vivado support memory initialization like ISE used to?

The RAM is defined and calls a function which uses a case statement to determine the initialization vector to initialize the RAM with:

constant c_mem_init_2d        : t_2d_memvector(0 to c_maxDEPTH-1, c_minWIDTH-1 downto 0) := sel_mem_array(g_mif_name, c_maxDEPTH, c_minWIDTH);  -- set value via package file
constant c_mem_init_arr_slv   :ram_type:= ram_type(To_Array_StdLogicVector(c_mem_init_2d));                                 -- Here we convert 2-D array and cast to type "array of slv" (t_RAM)
signal ram_name   : ram_type:= c_mem_init_arr_slv;


This style of initialization is not supported in Vivado.

It is recommended to initialize from an external data file to initialize the RAM.

AR# 65419
Date 09/16/2015
Status Active
Type General Article
  • Vivado Design Suite