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AR# 65447

DisplayPort RX Subsystem - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions

Description

This answer record contains the Release Notes and Known Issues for the DisplayPort RX Subsystem and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

DisplayPort RX Subsystem Page:

https://www.xilinx.com/content/xilinx/en/products/intellectual-property/ef-di-displayport.html

Solution

General Information

Supported Devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core Version Vivado Tools Version
v2.0 (Rev. 5) 2017.2
v2.0 (Rev. 4) 2017.1
v2.0 (Rev. 3) 2016.4
v2.0 (Rev. 2) 2016.3
v2.0 (Rev. 1) 2016.2
v2.0 2016.1
v1.0 2015.4

 

General Guidance

The table below provides Answer Records for general guidance when using the DisplayPort RX Subsystem.

Article Number Article Title
(Xilinx Answer 69077) XAPP1271 - Why does a debug build work but not the release build with optimizations?

 

Known and Resolved Issues

The following table provides known issues for the DisplayPort RX Subsystem, starting with v1.0, initially released in Vivado 2015.4.


Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

IP

Article Number Article Title Version Found Version Resolved
(Xilinx Answer 68860) Why do I get the warning message that the DisplayPort LogiCORE will become obsolete when I am already using the subsystem? v2.0 (Rev. 4) N/A
(Xilinx Answer 68908) Why does training succeed but there is no video data captured when using HDCP? v2.0 (Rev. 3) v2.0 (Rev. 4)
(Xilinx Answer 68431) How do I use the DP159 forwarded clock for 1.62 Gbps for the Kintex UltraScale parts? v2.0 (Rev. 3) v2.0 (Rev. 4)
(Xilinx Answer 68629) How do I support 3 EDID blocks? or How do I support an EDID larger than 256 bytes? v2.0 (Rev. 3) v2.0 (Rev. 4)
(Xilinx Answer 68454) Why does training timeout when using a DisplayPort Rx Subsystem MST design on some sources? v2.0 (Rev. 3) v2.0 (Rev. 4)
(Xilinx Answer 69199) Why does the OOC synthesis of the BD is always Out of date?
v2.0 (Rev. 2) v2.0 (Rev. 4)
(Xilinx Answer 67433) Why does the DisplayPort RX driver for the DisplayPort IP and DisplayPort subsystem sometimes fail to train when using the DP159 production silicon? v2.0 (Rev. 1) v2.0 (Rev. 3)


Software Driver

Article Number Article Title Version Found Version Resolved
(Xilinx Answer 67274) Why does the CP_CURRENT (0x02) register value differ between the documentation and the driver? v2.0 (Rev. 1) N/A


Revision History:

   
06/29/2017 Added v2.0 (Rev. 5) to Version Table and (XilinxAnswer 69199)
05/12/2017 Added v2.0 (Rev. 4) and v2.0 (Rev. 3) to Version Table (Xilinx Answer 68860) and (Xilinx Answer 69077)
02/07/2017 Added (Xilinx Answer 68454), (Xilinx Answer 68629), (Xilinx Answer 68431), v2.0 (Rev. 2) and v2.0 (Rev. 3) to Version Table
07/14/2016 Added (Xilinx Answer 67274), (Xilinx Answer 67433) and added v2.0 (Rev. 1) to Version Table
04/06/2016 Added v2.0 to Version Table
11/24/2015 Initial Release

 

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
56852 Xilinx Multimedia, Video and Imaging Solution Center - Top Issues N/A N/A

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
67432 Video Common Software Driver v3.0 - Video Common Software Driver v3.0 Patch Download N/A N/A
67433 LogiCORE DisplayPort Receiver v7.0 (Rev. 1) - XAPP1178 - XAPP1271 - Why does the DisplayPort RX driver for the DisplayPort IP and DisplayPort subsystem sometimes fail to train when using DP159 production silicon? N/A N/A
67274 LogiCORE DisplayPort Receiver v7.0 (Rev. 1) - Why does the CP_CURRENT (0x02) register value differ between the documentation and the driver? N/A N/A
68629 DisplayPort RX Subsystem v3.0 (Rev.3) - How do I support 3 EDID blocks? How do I support an EDID larger than 256 bytes? N/A N/A
68454 DisplayPort Receiver Subsystem v2.0 (Rev. 3) - Why does training timeout when using a DisplayPort Receiver Subsystem MST design on some sources? N/A N/A
68431 DisplayPort Receiver Subsystem v2.0 (Rev 3) - How do I use the DP159 forwarded clock for 1.62 Gbps for Kintex UltraScale parts? N/A N/A
68860 DisplayPort RX/TX Subsystem - Why do I get the warning message that the DisplayPort LogiCORE will become obsolete when I am already using the subsystem? N/A N/A
69077 XAPP1271 - Why does a debug build work but not the release build with optimizations? N/A N/A
68455 2016.4 DisplayPort Receiver Subsystem v2.0 (Rev. 3) - Patch updates for DisplayPort Receiver Subsystem v2.0 (Rev. 3) N/A N/A
68631 2016.4 DisplayPort Receiver Subsystem v2.0 (Rev. 3) - DisplayPort Software Driver v5.1 Patch Download N/A N/A
68685 2016.4 - LogiCORE Video PHY Controller Software Driver v1.3 - Patch Updates for the LogiCORE Video PHY Controller Software Driver v1.3 N/A N/A
69199 DisplayPort Subsystem - Why is the OOC synthesis of the BD always Out of date? N/A N/A

Associated Answer Records

AR# 65447
Date 07/10/2017
Status Active
Type Release Notes
IP
  • DisplayPort
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