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AR# 65447

DisplayPort RX Subsystem - Release Notes and Known Issues for Vivado 2015.4 and newer tool versions

Description

This answer record contains the Release Notes and Known Issues for the DisplayPort RX Subsystem and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

DisplayPort RX Subsystem Page:

https://www.xilinx.com/content/xilinx/en/products/intellectual-property/ef-di-displayport.html

Solution

General Information:

Supported Devices can be found in the following three locations:

For a list of new features and added device support for all versions:

  • Subsystem or IP - See the Changelog included with the core in Vivado.
  • Subsystem or IP - Click on the Changelog links below.
  • Standalone Software Drivers - See the Changelog included with the Doxygen Drivers in Xilinx SDK
  • Standalone Software Drivers - Github Software Driver Repo

Support:

Please seek technical support via the Video Board of the Xilinx Community Forums.

The Xilinx Forums are great resource for technical support. 

The entire Xilinx User Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.


Version Table:

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core VersionVivado Tools VersionSubsystem ChangelogSubsystem PatchesStandalone Software Driver Patches
v2.1 (Rev. 6)2019.2(Xilinx Answer 72923)
v2.1 (Rev. 5)2019.1(Xilinx Answer 72242)
v2.1 (Rev. 4)2018.3(Xilinx Answer 71806)
v2.1 (Rev. 3)2018.2(Xilinx Answer 71212)
v2.1 (Rev. 2)2018.1(Xilinx Answer 70699)
v2.1 (Rev. 1)2017.4(Xilinx Answer 70386)
v2.12017.3(Xilinx Answer 69903)
v2.0 (Rev. 5)2017.2(Xilinx Answer 69326)
v2.0 (Rev. 4)2017.1(Xilinx Answer 69055)
v2.0 (Rev. 3)2016.4(Xilinx Answer 68369)(Xilinx Answer 68455)(Xilinx Answer 68631)
v2.0 (Rev. 2)2016.3(Xilinx Answer 68021)
v2.0 (Rev. 1)
2016.2(Xilinx Answer 67345)
v2.02016.1(Xilinx Answer 66930)
v1.02015.4(Xilinx Answer 66004)

General Guidance:

The table below provides Answer Records for general guidance when using the DisplayPort RX Subsystem.

Article NumberArticle Title
(Xilinx Answer 71773)Does the DisplayPort Subsystems IPs support active or passive adaptors to HDMI, DVI or VGA?
(Xilinx Answer 71504)Why is the XAPP1271 not available anymore?
(Xilinx Answer 71499)What video resolutions are supported by the IP and can the IP support custom resolutions?
(Xilinx Answer 70130)Why does the video resolution not match between the GPU settings and the RX MSA registers?
(Xilinx Answer 69077)XAPP1271 - Why does a debug build work but not the release build with optimizations?
(Xilinx Answer 68639)Design Advisory for DisplayPort RX/TX Subsystems and LogiCORE Video PHY Controller - 7 Series GTHE2 and GTPE2 device support removed
(Xilinx Answer 68227)Video Common Library - How do I add support for custom resolutions to the Video Timing Table?

Known and Resolved Issues:

The following table provides known issues for the DisplayPort RX Subsystem, starting with v1.0, initially released in Vivado 2015.4.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

IP:

Article NumberArticle TitleVersion FoundVersion Resolved
(Xilinx Answer 70538)The AXI4-Stream interface is not following the specification for the data width v2.1N/A
(Xilinx Answer 69421)7 Series: The CPLL must be powered down when not in usev2.0N/A
(Xilinx Answer 69199)Why is the OOC synthesis of the BD always Out of date?v2.0 (Rev. 2)v2.0 (Rev. 4)
(Xilinx Answer 68860)Why do I get the warning message that the DisplayPort LogiCORE will become obsolete when I am already using the subsystem? v2.0 (Rev. 4)N/A
(Xilinx Answer 68908) Why does training succeed but there is no video data captured when using HDCP? v2.0 (Rev. 3)v2.0 (Rev. 4)
(Xilinx Answer 68431) How do I use the DP159 forwarded clock for 1.62 Gbps for the Kintex UltraScale parts? v2.0 (Rev. 3)v2.0 (Rev. 4)
(Xilinx Answer 68629)How do I support 3 EDID blocks? or How do I support an EDID larger than 256 bytes?v2.0 (Rev. 3)v2.0 (Rev. 4)
(Xilinx Answer 68454)Why does training time out when using a DisplayPort RX Subsystem MST design on some sources?v2.0 (Rev. 3)v2.0 (Rev. 4)
(Xilinx Answer 67433)Why does the DisplayPort RX driver for the DisplayPort IP and DisplayPort subsystem sometimes fail to train when using the DP159 production silicon?v2.0 (Rev. 1)v2.0 (Rev. 3)

Software Driver:

Article NumberArticle TitleVersion FoundVersion Resolved
(Xilinx Answer 67274)Why does the CP_CURRENT (0x02) register value differ between the documentation and the driver?v2.0 (Rev. 1)v2.0 (Rev. 2)

Example Design:
Article NumberArticle TitleVersion FoundVersion Resolved
(Xilinx Answer 72221)The KCU105 example design application displays color disruption on monitor in pass-through mode v2.1 (Rev.2)v2.1 (Rev. 5)
(Xilinx Answer 70328)Why can an example design integrated in Vivado not be built on Windows? v2.1
v2.1 (Rev. 4)

 

Revision History:
06/21/2019Added (Xilinx Answer 72242) to Version table
04/19/2019Added v2.1 (Rev. 5) and (Xilinx Answer 71806) to Version table and (Xilinx Answer 72221) to example design known issues table
11/30/2018Added v2.1 (Rev. 4) to Version table and (Xilinx Answer 71773) to General Guidance Table
10/24/2018Created table for Example Design known issues and added (Xilinx Answer 70328)
08/31/2018Added (Xilinx Answer 71499) and (Xilinx Answer 71504)  to General Guidance and v2.1 (Rev. 3) to version table
04/04/2018Added v2.1 (Rev. 2) to Version Table
03/02/2018Added v2.1 (Rev.1) to Version Table, (Xilinx Answer 70130), (Xilinx Answer 68227), (Xilinx Answer 68639) and (Xilinx Answer 70538)
11/13/2017Added v2.1 to Version Table
08/21/2017Added (Xilinx Answer 69421)
06/29/2017Added (Xilinx Answer 69199)
05/12/2017Added v2.0 (Rev. 3) to Version Table (Xilinx Answer 68860) and (Xilinx Answer 69077)
02/07/2017Added (Xilinx Answer 68454), (Xilinx Answer 68629), (Xilinx Answer 68431), v2.0 (Rev. 2) to Version Table
07/14/2016Added (Xilinx Answer 67274), (Xilinx Answer 67433) and added v2.0 (Rev. 1) to Version Table
04/06/2016Added v2.0 to Version Table
11/24/2015Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
56852 Xilinx Multimedia, Video and Imaging Solution Center - Top Issues N/A N/A

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
67432 Video Common Software Driver v3.0 - Video Common Software Driver v3.0 Patch Download N/A N/A
67433 LogiCORE DisplayPort Receiver v7.0 (Rev. 1) - XAPP1178 - XAPP1271 - Why does the DisplayPort RX driver for the DisplayPort IP and DisplayPort subsystem sometimes fail to train when using DP159 production silicon? N/A N/A
67274 LogiCORE DisplayPort Receiver v7.0 (Rev. 1) - Why does the CP_CURRENT (0x02) register value differ between the documentation and the driver? N/A N/A
68629 DisplayPort RX Subsystem v2.0 (Rev.3) - How do I support 3 EDID blocks? How do I support an EDID larger than 256 bytes? N/A N/A
68454 DisplayPort Receiver Subsystem v2.0 (Rev. 3) - Why does training timeout when using a DisplayPort Receiver Subsystem MST design on some sources? N/A N/A
68431 DisplayPort Receiver Subsystem v2.0 (Rev 3) - How do I use the DP159 forwarded clock for 1.62 Gbps for Kintex UltraScale parts? N/A N/A
68860 DisplayPort RX/TX Subsystem - Why do I get the warning message that the DisplayPort LogiCORE will become obsolete when I am already using the subsystem? N/A N/A
69077 XAPP1271 - Why does a debug build work but not the release build with optimizations? N/A N/A
68455 2016.4 DisplayPort Receiver Subsystem v2.0 (Rev. 3) - Patch updates for DisplayPort Receiver Subsystem v2.0 (Rev. 3) N/A N/A
68631 2016.4 DisplayPort Receiver Subsystem v2.0 (Rev. 3) - DisplayPort Software Driver v5.1 Patch Download N/A N/A
68685 2016.4 - LogiCORE Video PHY Controller Software Driver v1.3 - Patch Updates for the LogiCORE Video PHY Controller Software Driver v1.3 N/A N/A
69199 DisplayPort Subsystem - Why is the OOC synthesis of the BD always Out of date? N/A N/A
69421 DisplayPort RX Subsystem - 7 Series: The CPLL must be powered down when not in use N/A N/A
68639 Design Advisory for DisplayPort RX/TX Subsystems and LogiCORE Video PHY Controller - 7 Series GTHE2 and GTPE2 device support removed N/A N/A
67091 2017.2 LogiCORE DisplayPort TX Subsystem 2.0 (Rev. 3) - Patch Updates for the DisplayPort TX Subsystem v2.0 (Rev. 3) N/A N/A
70130 DisplayPort RX Subsystem - Why does the video resolution not match between the GPU settings and the RX MSA registers? N/A N/A
70328 DisplayPort RX/TX Subsystem - Why can the example design integrated in Vivado not be built on Windows? N/A N/A
70715 DisplayPort TX/RX Subsystem - Why do I see a difference in the Subsystem AXI4-Interface pixel packing and the Video over AXI4-Interface pixel mapping definition in UG934? N/A N/A
71499 DisplayPort RX Subsystem IP - What video resolutions are supported by the IP and can the IP support custom resolutions? N/A N/A
71504 DisplayPort TX/RX Subsystem - Why is XAPP1271 not available anymore? N/A N/A
71773 DisplayPort TX/RX Subsystem - Do the DisplayPort Subsystems IPs support active or passive adaptors to HDMI, DVI, or VGA? N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
59384 DisplayPort TX Subsystem - Release Notes and Known Issues for Vivado 2015.4 and newer tool versions N/A N/A
54522 LogiCORE IP DisplayPort - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
57842 LogiCORE Video PHY Controller - Release Notes and Known Issues for Vivado 2015.4 and newer tool versions N/A N/A
AR# 65447
Date 01/14/2020
Status Active
Type Release Notes
IP