UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 65449

LogiCORE IP Video Processing Subsystem(VPSS) - Release Notes and Known Issues for the Vivado 2015.3 tool and later versions

Description

This answer record contains the Release Notes and Known Issues for the Video Processing Subsystem Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

Video Processing Subsystem Page:

https://www.xilinx.com/products/intellectual-property/video-processing-subsystem.html

Solution

General Information:


Supported Devices can be found in the following three locations:

For a list of new features and added device support for all versions:

  • Subsystem or IP - See the Changelog included with the core in Vivado.
  • Subsystem or IP - Click on the Changelog links below.
  • Standalone Software Drivers - See the Changelog included with the Doxygen Drivers in Xilinx SDK
  • Standalone Software Drivers - Github Software Driver Repo
  • Linux Drivers - Xilinx Wiki (Search for VPSS)

Please seek technical support via the Video Board of the Xilinx Community Forums.

The Xilinx Forums are a great resource for technical support. 

The entire Xilinx User Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.


Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core VersionVivado Tools VersionSubsystem ChangelogIP PatchesStandalone Software Driver Patches
v2.12019.1(Xilinx Answer 72242)
v2.0 (Rev. 10)2018.3(Xilinx Answer 71806)
v2.0 (Rev. 9)2018.2(Xilinx Answer 71212)
v2.0 (Rev. 8)2018.1(Xilinx Answer 70699)(Xilinx Answer 67186)
v2.0 (Rev. 7)2017.4(Xilinx Answer 70386)(Xilinx Answer 67186)
v2.0 (Rev. 6)2017.3(Xilinx Answer 69903)
v2.0 (Rev. 5)2017.2(Xilinx Answer 69326)
v2.0 (Rev. 4)2017.1(Xilinx Answer 69055)
v2.0 (Rev. 3)2016.4(Xilinx Answer 68369)
v2.0 (Rev. 2)2016.3(Xilinx Answer 68021)(Xilinx Answer 68199)
v2.0 (Rev. 1)2016.2(Xilinx Answer 67345)(Xilinx Answer 67375)
v2.02016.1(Xilinx Answer 66930)
v1.02015.3(Xilinx Answer 65570)

General Guidance

The table below provides Answer Records for general guidance when using the LogiCORE Video Processing Subsystem.

Article NumberArticle Title
(Xilinx Answer 72233)PG231 - Why does the SDK project for the example design fail to generate in 2018.3 and later?
(Xilinx Answer 71950)
Can I use the VPSS for 8K resolutions in 2018.3?
(Xilinx Answer 71759)Why do I get the error "ERROR: [HLS 200-101] 'add_files': Too many positional arguments specified." when using HLS Based Video IPs?
(Xilinx Answer 66692)Core fails to generate properly
(Xilinx Answer 66435)Clarification of color space mappings

Known and Resolved Issues

The following table provides known issues for the Video Processing Subsystem, starting with v1.0, initially released in Vivado 2015.3.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Table 3: IP

Article NumberArticle TitleVersion FoundVersion Resolved
(Xilinx Answer 72427)Why do I see visual artifacts from the scaler when using UltraRAM?v2.0 (Rev. 7)v2.0 (Rev. 9)
(Xilinx Answer 70421)Why do I see synthesis failures when using Windows OS for synthesis?v2.0 (Rev. 6)N/A
(Xilinx Answer 65800)Example design fails to meet timing inside the IPv1.0v2.0

Table 4: Software Driver

Article NumberArticle TitleVersion FoundVersion Resolved
(Xilinx Answer 65562)Why does the output color rate not update correctly when using the Color Space Conversion feature?v2.0 (Rev. 7)N/A
(Xilinx Answer 68756)Why does the Video Subsystem fail to configure when using a custom resolution?v2.0 (Rev. 3)v2.0 (Rev. 4)
(Xilinx Answer 68212)Why is the TVALID deasserted and there is no output when using the VPSS in full-fledged mode, with the input set as RGB and the output set as YCbCr 4:2:2 or 4:2:0?v2.0 (Rev. 2)v2.0 (Rev. 3)
(Xilinx Answer 67431)Driver Support for Multiple VPSS Instancesv2.0v2.0 (Rev. 2)


Revision History:
06/04/2019Added (Xilinx Answer 72427) to Known issues table
05/22/2019Added to v2.1 to revision table and (Xilinx Answer 71950) to General Guidance table
01/07/2019Added System changelog link for 2018.3.
11/28/2018Added v2.0 (Rev. 9) and v2.0 (Rev. 10) to Version Table and (Xilinx Answer 71759) to General Guidance
06/07/2018Added (Xilinx Answer 65562)
04/24/2018Added (Xilinx Answer 68212), (Xilinx Answer 68756) and (Xilinx Answer 67186)
04/04/2018Added v2.0 (Rev. 8) to Version Table
01/17/2018Added v2.0 (Rev. 6) and v2.0 (Rev. 7) to Version Table and (Xilinx Answer 70421)
06/29/2017Added v2.0 (Rev. 2), v2.0 (Rev. 3), v2.0 (Rev. 4) and v2.0 (Rev. 5) to Version Table
02/08/2017Added v2.0 (Rev. 1) to Version Table and added (Xilinx Answer 67431)
07/05/2016Added (Xilinx Answer 68716)
04/06/2016Added v2.0 to Version Table.
03/07/2016Added (Xilinx Answer 66692)
03/02/2016Fixed links
01/19/2016Added (Xilinx Answer 66435)
10/28/2015Fixed typo, added (Xilinx Answer 65800)
09/30/2015Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
56852 Xilinx Multimedia, Video and Imaging Solution Center - Top Issues N/A N/A

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
65800 LogiCORE IP Video Processing Subsystem v1.0 - Example design fails to meet timing inside the IP N/A N/A
66435 LogiCORE IP Video Processing Subsystem v1.0 - Clarification of color space mappings N/A N/A
66692 LogiCORE IP Video Processing Subsystem v1.0 - Core fails to generate properly N/A N/A
67431 LogiCORE IP Video Processing Subsystem, Software Driver V2.0 - Driver Support for Multiple VPSS Instances N/A N/A
68716 LogiCORE IP Video Processing Subsystem (VPSS) v2.0 - Why do I see timing failures due to too many layers of logic? N/A N/A
70421 LogiCORE IP Test Pattern Generator (TPG) and LogiCORE IP Video Processing Subsystem (VPSS) - Why do I see synthesis failures when using a Windows OS for synthesis? N/A N/A
70445 2017.4 Vivado HLS - Windows OS - Missing ports in the generated RTL when using hls::stream interfaces N/A N/A
68212 LogiCORE IP Video Processing Subsystem (VPSS), Software Driver v2.1 - Why is the TVALID deasserted and there no output when using the VPSS in full-fledged mode, when input is set as RGB selected and the output is set as YCbCr 4:2:2 or 4:2:0? N/A N/A
68199 LogiCORE IP Video Processing Subsystem, Software Driver v2.1 - Video Processing Subsystem Software Driver v2.1 Patch Download N/A N/A
68756 LogiCORE IP Video Processing Subsystem v2.0 - Why does the Video Subsystem fail to configure when using a custom resolution? N/A N/A
67186 2017.4 and 2018.1 LogiCORE IP Video Processing Subsystem, Software Driver v2.2 - Video Processing Subsystem Software Driver v2.2 Patch Download N/A N/A
71759 Why do I get the error "ERROR: [HLS 200-101] 'add_files': Too many positional arguments specified." when using HLS Based Video IPs N/A N/A
AR# 65449
Date 06/07/2019
Status Active
Type Release Notes
IP
Page Bookmarked