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AR# 65449

LogiCORE IP Video Processing Subsystem - Release Notes and Known Issues for the Vivado 2015.3 tool and later versions

Description

This answer record contains the Release Notes and Known Issues for the Video Processing Subsystem Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

LogiCORE Video Processing Subsystem Page:

https://www.xilinx.com/products/intellectual-property/video-processing-subsystem.html

Solution

General Information:


Supported Devices can be found in the following three locations:

For a list of new features and added device support for all versions:

  • Subsystem or IP - See the Changelog included with the core in Vivado.
  • Subsystem or IP - Click on the Changelog links below.
  • Standalone Software Drivers - See the Chagelog included with the Doxygen Drivers in Xilinx SDK
  • Standalone Software Drivers - Github Software Driver Repo
  • Linux Drivers - Xilinx Wiki (Search for VPSS)


Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core VersionVivado Tools Version Subsystem Changelog
v2.0 (Rev 8)2018.1
v2.0 (Rev. 7)2017.4(Xilinx Answer 70386)
v2.0 (Rev. 6)2017.3(Xilinx Answer 69903)
v2.0 (Rev. 5)2017.2(Xilinx Answer 69326)
v2.0 (Rev. 4)2017.1(Xilinx Answer 69055)
v2.0 (Rev. 3)2016.4(Xilinx Answer 68369)
v2.0 (Rev. 2)2016.3(Xilinx Answer 68021)
v2.0 (Rev. 1)2016.2(Xilinx Answer 67345)
v2.02016.1(Xilinx Answer 66930)
v1.02015.3(Xilinx Answer 65570)

General Guidance

The table below provides Answer Records for general guidance when using the LogiCORE Video Processing Subsystem.

Article NumberArticle Title
(Xilinx Answer 66692)Core fails to generate properly
(Xilinx Answer 66435)Clarification of color space mappings

Known and Resolved Issues

The following table provides known issues for the Video Processing Subsystem, starting with v1.0, initially released in Vivado 2015.3.

Note: The "Version Found" column lists the version the problem was first discovered. 

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Table 3: IP
Article NumberArticle TitleVersion FoundVersion Resolved
(Xilinx Answer 70421)Why do I see synthesis failures when using Windows OS for synthesis?v2.0 (Rev. 6)N/A
(Xilinx Answer 65800)Example design fails to meet timing inside the IPv1.0v2.0

Table 4: Software Driver
Article NumberArticle TitleVersion FoundVersion Resolved
(Xilinx Answer 67431)Driver Support for Multiple VPSS Instancesv2.0N/A


Revision History:

04/04/2018Added v2.0 (Rev. 8) to Version Table
01/17/2018Added v2.0 (Rev. 6) and v2.0 (Rev. 7) to Version Table and (Xilinx Answer 70421)
06/29/2017Added v2.0 (Rev. 2), v2.0 (Rev. 3), v2.0 (Rev. 4) and v2.0 (Rev. 5) to Version Table
02/08/2017Added v2.0 (Rev. 1) to Version Table and added (Xilinx Answer 67431)
07/05/2016Added (Xilinx Answer 68716)
04/06/2016Added v2.0 to Version Table.
03/07/2016Added (Xilinx Answer 66692)
03/02/2016Fixed links
01/19/2016Added (Xilinx Answer 66435)
10/28/2015Fixed typo, added (Xilinx Answer 65800)
09/30/2015Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
56852 Xilinx Multimedia, Video and Imaging Solution Center - Top Issues N/A N/A

Child Answer Records

AR# 65449
Date 04/09/2018
Status Active
Type Release Notes
IP
  • Video Scaler
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