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AR# 65462

AXI Bridge for PCI Express Gen3 Subsystem v2.0 (Vivado 2015.3) - Link Up Bit (Bit[11]) in Phy Status Register is Not Asserted

Description

Version Found: v2.0

Version Resolved and other Known Issues: See (Xilinx Answer 6189

When the link is operational, Link Up bit (bit[11]) in Phy Status register does not assert.

Solution

The link up signal was connected to the wrong bit order, bit[9] instead of bit[11].

This will be corrected in the next release of the core.


Note: "Version Found" refers to the version where the problem was first discovered.

The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.


Revision History:

10/06/2015 - Initial Release

AR# 65462
Date Created 09/21/2015
Last Updated 10/07/2015
Status Active
Type General Article
IP
  • AXI PCIe Gen3