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AR# 65468

Zynq UltraScale+ MPSoC - Booting a Zynq UltraScale+ MPSoC Device

Description

This answer record is a documentation map providing information about booting a Zynq UltraScale+ MPSoC device.

It links to documents which cover different modes and configurations for booting a Zynq UltraScale+ MPSoC device using your boot interface of choice. 


Note: This answer record is part of Xilinx Zynq UltraScale+ MPSoC Solution Center (Xilinx Answer 64375).

The Xilinx Zynq UltraScale+ MPSoC Solution Center is available to address all questions related to Zynq UltraScale+ MPSoC.

Whether you are starting a new design or troubleshooting a problem, use the Zynq UltraScale+ MPSoC Solution Center to guide you to the right information.

Solution

Boot Flows and Concepts (FSBL, image creation through BootGEN, multiboot, and fallback mechanisms) are described in 

  • Chapters 9 and 10 of (UG1085) Zynq UltraScale+ MPSoC Technical Reference Manual
  • Chapter 7, chapter 8, and appendix A of (UG1137) Zynq UltraScale+ MPSoC Software Developer Guide.

Below are some more Xilinx Answers relevant for Boot and Configuration.

Primary Boot Devices

Zynq UltraScale+ MPSoC supports Quad-SPI, NAND, SD, and eMMC as primary boot interfaces.

(Xilinx Answer 65463) contains details about which memory vendors and devices families are tested and supported by Xilinx.

AR# 65468
Date Created 09/22/2015
Last Updated 12/04/2015
Status Active
Type General Article
Devices
  • Zynq UltraScale+ MPSoC