We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 65493

DDR4/3 UltraScale - IP generation fails for configurations requiring more than 3 contiguous banks when targetting FGPA devices with half banks in between full banks


Version Found: v1.0

Version Resolved: See (Xilinx Answer 58435)

When trying to generate a DDR4/3 configuration requiring more than 3 contiguous banks in a target FPGA that has half banks in between full banks, errors similar to the following are generated:

[#undef] There are certain ports which are still unassigned as per the selected data width 72, design generation can be done correctly once all the bytes/sites are assigned.

Configurations that require more than 3 contiguous banks are:

  1. 80-bit interfaces
  2. 72-bit, dual slot, dual rank interfaces

An example of a device that would see this error is the xcku095-ffvb2104-3-e which has 5 contiguous banks 65, 66,67,68,69 in the right column with a half bank (68) in between.


While this configuration is valid, the DDR4/3 wizard is not counting the half bank as a contiguous bank and therefore failing IP generation.

This issue is planned to be resolved with Vivado 2016.1.

If assistance is needed before this time, please open a webcase.

AR# 65493
Date 10/20/2015
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • MIG UltraScale