Version Found: DDR4 v1.0, DDR3 v1.0
When trying to generate a DDR4/3 configuration requiring more than 3 contiguous banks in a target FPGA that has half banks in between full banks, errors similar to the following are generated:
Configurations that require more than 3 contiguous banks are:
An example of a device that would see this error is the xcku095-ffvb2104-3-e which has 5 contiguous banks 65, 66,67,68,69 in the right column with a half bank (68) in between.
While this configuration is valid, the DDR4/3 wizard is not counting the half bank as a contiguous bank and therefore failing IP generation.
This issue is planned to be resolved in Vivado 2016.1.
If assistance is needed before this time, please open a Service Request.