I have created a design in Vivado 2015.1 that I upgraded to Vivado 2015.2 or Vivado 2015.3.
Two customizations of the AXI Interconnect did not upgrade and have the following status in the IP status report:
I would expect to only see the IP Revision Change listed and be able to upgrade the AXI Interconnect from 2.1 Rev 5 to 2.1 Rev 6.
The root cause of this issue is that an IPI-only core is appearing in an IP Project.
The AXI Interconnect is only designed for use within a block diagram, and does not generate any synthesis outputs.
When the BD is packaged, the XCI files for AppCores should be omitted.
Each AXI Interconnect v2.1 is being added to the project twice. Once in HDL-form as part of system.v, and again as an XCI file that will generate no outputs, but cause problems in "Report IP Status".
The unnecessary XCI files can be removed with the following command:
remove_files [get_files myAppCore.xci]
The project will then upgrade successfully, and proceed to generation without problems.
An example command to remove the core is:
remove_files [get_files system_axi_mem_intercon_0.xci]
In Vivado 2015.3 the following changes have been made