My design fails during BitGen with the below error in Vivado 2015.1:
Below is the output of the report_route_status command executed on the Implemented design:
The unrouted pins are the I pins of OBUFT instances. The T pin of these OBUFT instances are driven from FDRE which has conflicting constraints, i.e., IOB=FALSE and LOC=OLOGIC_XxYy.
As a result the tool is placing these FDRE instances at the OUTFF BEL in the OLOGIC site which is incorrect.
Either of the below work-arounds can be used:
1. Change the IOB property to TRUE on the flop.
2. Use the below BEL constraints to lock the FDRE at the TFF BEL instead:
set_property BEL TFF [get_cells blackbird_system_wrapper1/blackbird_system_i/axi_quad_spi_cfg/U0/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/SPI_TRISTATE_CONTROL_III]
set_property BEL TFF [get_cells blackbird_system_wrapper1/blackbird_system_i/axi_quad_spi_1/U0/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/SPI_TRISTATE_CONTROL_III]